Re: [PATCH v4 6/6] hw/ssi: imx_spi: Correct tx and rx fifo endianness

[Philippe Mathieu-Daudé]

On 1/12/21 1:48 PM, Bin Meng wrote:
> On Tue, Jan 12, 2021 at 6:46 PM Peter Maydell <peter.maydell@linaro.org> 
> wrote:
>>
>> On Sun, 10 Jan 2021 at 08:15, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>
>>> From: Bin Meng <bin.meng@windriver.com>
>>>
>>> The endianness of data exchange between tx and rx fifo is incorrect.
>>> Earlier bytes are supposed to show up on MSB and later bytes on LSB,
>>> ie: in big endian. The manual does not explicitly say this, but the
>>> U-Boot and Linux driver codes have a swap on the data transferred
>>> to tx fifo and from rx fifo.
[...]
>>
>> This version of the loop definitely looks a lot neater. However,
>> looking at the code I don't think there's anything that forces the
>> guest to set a burst length that's a multiple of 8, so you need
>> to handle that somehow. Otherwise on the last time through the
>> loop (tx_burst - 8) can be negative, which is undefined behaviour
>> when you try to shift by it.
> 
> Yes, that's why I added a patch to log the unimplemented behavior to
> notify the user.
> 
>> I think just rounding tx_burst up to a multiple of 8 before
>> the start of the loop would do the right thing ?
> 
> Probably. Given all flash transfers are normally multiple of 8-bits I
> am not sure what the real hardware behavior is when it is not multiple
> of 8, but I will try to add something in the next version.

FWIW not multiple of 8 use is not that uncommon, see:
https://guruce.com/blogpost/freescale-imx53-and-imx6-ecspi-silicon-bug