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Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi mode
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model |
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Date: |
Sat, 16 Jan 2021 22:03:59 +0800 |
Hi Philippe,
On Fri, Jan 15, 2021 at 11:31 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi,
>
> This is how I understand the ecSPI reset works, after
> looking at the IMX6DQRM.pdf datasheet.
>
> This is a respin of Ben's v5 series [*].
>
> Since v6:
> - Dropped "Reduce 'change_mask' variable scope" patch
> - Fixed inverted reset logic
> - Added Juan R-b tags
> - Removed 'RFC' tag as tests pass
>
> Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com>
> (queued on riscv-next).
>
This series dropped my imx_spi_soft_reset() change that has the
imx_spi_update_irq() moved from imx_spi_reset(). May I know why?
Regards,
Bin
- [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, (continued)
[PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled, Philippe Mathieu-Daudé, 2021/01/15
[PATCH v7 7/9] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Philippe Mathieu-Daudé, 2021/01/15
[PATCH v7 8/9] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Philippe Mathieu-Daudé, 2021/01/15
[PATCH v7 9/9] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Philippe Mathieu-Daudé, 2021/01/15
Re: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model,
Bin Meng <=