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[PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller i
From: |
Bin Meng |
Subject: |
[PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled |
Date: |
Tue, 19 Jan 2021 21:39:03 +0800 |
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, but chip select
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its last state and responds incorrectly to any follow-up commands.
Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller")
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
(no changes since v3)
Changes in v3:
- Move the chip selects disable out of imx_spi_reset()
Changes in v2:
- Fix the "Fixes" tag in the commit message
hw/ssi/imx_spi.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 23f9f9d..5838bb0 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -257,9 +257,15 @@ static void imx_spi_reset(DeviceState *dev)
static void imx_spi_soft_reset(IMXSPIState *s)
{
+ int i;
+
imx_spi_reset(DEVICE(s));
imx_spi_update_irq(s);
+
+ for (i = 0; i < ECSPI_NUM_CS; i++) {
+ qemu_set_irq(s->cs_lines[i], 1);
+ }
}
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
--
2.7.4
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, (continued)
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Bin Meng, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Bin Meng, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Philippe Mathieu-Daudé, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Philippe Mathieu-Daudé, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Peter Maydell, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Philippe Mathieu-Daudé, 2021/01/28
- Re: [PATCH v8 04/10] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value, Bin Meng, 2021/01/28
[PATCH v8 05/10] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Bin Meng, 2021/01/19
[PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled,
Bin Meng <=
[PATCH v8 06/10] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, Bin Meng, 2021/01/19
[PATCH v8 09/10] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Bin Meng, 2021/01/19
[PATCH v8 08/10] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Bin Meng, 2021/01/19
[PATCH v8 10/10] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Bin Meng, 2021/01/19
Re: [PATCH v8 00/10] hw/ssi: imx_spi: Fix various bugs in the imx_spi model, Bin Meng, 2021/01/22