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[PATCH v2 3/3] tests/qtest: Add test for Aspeed HACE
|
From: |
Joel Stanley |
|
Subject: |
[PATCH v2 3/3] tests/qtest: Add test for Aspeed HACE |
|
Date: |
Fri, 12 Mar 2021 10:17:26 +1030 |
This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.
The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
test fails.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/qtest/aspeed_hace-test.c | 215 +++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 3 +
3 files changed, 219 insertions(+)
create mode 100644 tests/qtest/aspeed_hace-test.c
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
new file mode 100644
index 000000000000..52501ee37afb
--- /dev/null
+++ b/tests/qtest/aspeed_hace-test.c
@@ -0,0 +1,215 @@
+/*
+ * QTest testcase for the ASPEED Hash and Crypto Engine
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright 2021 IBM Corp.
+ */
+
+#include "qemu/osdep.h"
+
+#include "libqtest-single.h"
+#include "qemu-common.h"
+#include "qemu/bitops.h"
+
+#define HACE_BASE 0x1e6d0000
+
+#define HACE_CMD 0x10
+#define HACE_SHA_BE_EN BIT(3)
+#define HACE_MD5_LE_EN BIT(2)
+#define HACE_ALGO_MD5 0
+#define HACE_ALGO_SHA1 BIT(5)
+#define HACE_ALGO_SHA224 BIT(6)
+#define HACE_ALGO_SHA256 (BIT(4) | BIT(6))
+#define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
+#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
+#define HACE_SG_EN BIT(18)
+
+#define HACE_STS (HACE_BASE + 0x1c)
+#define HACE_RSA_ISR BIT(13)
+#define HACE_CRYPTO_ISR BIT(12)
+#define HACE_HASH_ISR BIT(9)
+#define HACE_RSA_BUSY BIT(2)
+#define HACE_CRYPTO_BUSY BIT(1)
+#define HACE_HASH_BUSY BIT(0)
+#define HACE_HASH_SRC (HACE_BASE + 0x20)
+#define HACE_HASH_DIGEST (HACE_BASE + 0x24)
+#define HACE_HASH_KEY_BUFF (HACE_BASE + 0x28)
+#define HACE_HASH_DATA_LEN (HACE_BASE + 0x2c)
+#define HACE_HASH_CMD (HACE_BASE + 0x30)
+
+QTestState *qts;
+
+/*
+ * Test vector is the ascii "abc"
+ *
+ * Expected results were generated using command line utitiles:
+ *
+ * echo -n -e 'abc' | dd of=/tmp/test
+ * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done
+ *
+ */
+static const uint8_t test_vector[] = {0x61, 0x62, 0x63};
+
+static const uint8_t test_result_sha512[] = {
+ 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
+ 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
+ 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
+ 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
+ 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
+ 0xa5, 0x4c, 0xa4, 0x9f};
+
+static const uint8_t test_result_sha256[] = {
+ 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde,
+ 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
+ 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
+
+static const uint8_t test_result_md5[] = {
+ 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d,
+ 0x28, 0xe1, 0x7f, 0x72};
+
+static void write_regs(uint64_t src, uint64_t length, uint64_t out,
+ uint32_t method)
+{
+ writel(HACE_HASH_SRC, src);
+ writel(HACE_HASH_DIGEST, out);
+ writel(HACE_HASH_DATA_LEN, length);
+ writel(HACE_HASH_CMD, HACE_SHA_BE_EN | method);
+}
+
+static void test_md5(void)
+{
+ uint64_t src_addr = 0x80000000;
+ uint64_t digest_addr = 0x81000000;
+ uint8_t digest[16] = {0};
+
+ /* Check engine is idle, no busy or irq bits set */
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Write test vector into memory */
+ qtest_memwrite(qts, src_addr, test_vector, sizeof(test_vector));
+
+ write_regs(src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5);
+
+ /* Check hash IRQ status is asserted */
+ g_assert_cmphex(readl(HACE_STS), ==, 0x00000200);
+
+ /* Clear IRQ status and check status is deasserted */
+ writel(HACE_STS, 0x00000200);
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Read computed digest from memory */
+ qtest_memread(qts, digest_addr, digest, sizeof(digest));
+
+ /* Check result of computation */
+ g_assert_cmpmem(digest, sizeof(digest),
+ test_result_md5, sizeof(digest));
+}
+
+static void test_sha256(void)
+{
+ uint64_t src_addr = 0x80000000;
+ uint64_t digest_addr = 0x81000000;
+ uint8_t digest[32] = {0};
+
+ /* Check engine is idle, no busy or irq bits set */
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Write test vector into memory */
+ qtest_memwrite(qts, src_addr, test_vector, sizeof(test_vector));
+
+ write_regs(src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256);
+
+ /* Check hash IRQ status is asserted */
+ g_assert_cmphex(readl(HACE_STS), ==, 0x00000200);
+
+ /* Clear IRQ status and check status is deasserted */
+ writel(HACE_STS, 0x00000200);
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Read computed digest from memory */
+ qtest_memread(qts, digest_addr, digest, sizeof(digest));
+
+ /* Check result of computation */
+ g_assert_cmpmem(digest, sizeof(digest),
+ test_result_sha256, sizeof(digest));
+}
+
+static void test_sha512(void)
+{
+ uint64_t src_addr = 0x80000000;
+ uint64_t digest_addr = 0x81000000;
+ uint8_t digest[64] = {0};
+
+ /* Check engine is idle, no busy or irq bits set */
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Write test vector into memory */
+ qtest_memwrite(qts, src_addr, test_vector, sizeof(test_vector));
+
+ write_regs(src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512);
+
+ /* Check hash IRQ status is asserted */
+ g_assert_cmphex(readl(HACE_STS), ==, 0x00000200);
+
+ /* Clear IRQ status and check status is deasserted */
+ writel(HACE_STS, 0x00000200);
+ g_assert_cmphex(readl(HACE_STS), ==, 0);
+
+ /* Read computed digest from memory */
+ qtest_memread(qts, digest_addr, digest, sizeof(digest));
+
+ /* Check result of computation */
+ g_assert_cmpmem(digest, sizeof(digest),
+ test_result_sha512, sizeof(digest));
+}
+
+static void test_addresses(void)
+{
+ /*
+ * Check command mode is zero, meaning engine is in direct access mode,
+ * as this affects the masking behavior of the HASH_SRC register.
+ */
+ g_assert_cmphex(readl(HACE_CMD), ==, 0);
+ g_assert_cmphex(readl(HACE_HASH_SRC), ==, 0);
+ g_assert_cmphex(readl(HACE_HASH_DIGEST), ==, 0);
+ g_assert_cmphex(readl(HACE_HASH_DATA_LEN), ==, 0);
+
+ /* Check that the address masking is correct */
+ writel(HACE_HASH_SRC, 0xffffffff);
+ g_assert_cmphex(readl(HACE_HASH_SRC), ==, 0x7fffffff);
+
+ writel(HACE_HASH_DIGEST, 0xffffffff);
+ g_assert_cmphex(readl(HACE_HASH_DIGEST), ==, 0x7ffffff8);
+
+ writel(HACE_HASH_DATA_LEN, 0xffffffff);
+ g_assert_cmphex(readl(HACE_HASH_DATA_LEN), ==, 0x0fffffff);
+
+ /* Reset to zero */
+ writel(HACE_HASH_SRC, 0);
+ writel(HACE_HASH_DIGEST, 0);
+ writel(HACE_HASH_DATA_LEN, 0);
+
+ /* Check that all bits are now zero */
+ g_assert_cmphex(readl(HACE_HASH_SRC), ==, 0);
+ g_assert_cmphex(readl(HACE_HASH_DIGEST), ==, 0);
+ g_assert_cmphex(readl(HACE_HASH_DATA_LEN), ==, 0);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ qtest_add_func("aspeed_hace_addresses", test_addresses);
+ qtest_add_func("aspeed_hace_sha512", test_sha512);
+ qtest_add_func("aspeed_hace_sha256", test_sha256);
+ qtest_add_func("aspeed_hace_md5", test_md5);
+
+ qts = qtest_start("-machine ast2600-evb");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index e04ae21a2f04..353aa479a720 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1026,6 +1026,7 @@ F: include/hw/misc/pca9552*.h
F: hw/net/ftgmac100.c
F: include/hw/net/ftgmac100.h
F: docs/system/arm/aspeed.rst
+F: tests/qtest/*aspeed*
NRF51
M: Joel Stanley <joel@jms.id.au>
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 2688e1bfad7f..2eec06b10094 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -156,12 +156,15 @@ qtests_npcm7xx = \
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test'] + \
(slirp.found() ? ['npcm7xx_emc-test'] : [])
+qtests_aspeed = \
+ ['aspeed_hace-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ?
['cmsdk-apb-dualtimer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ?
['cmsdk-apb-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ?
['cmsdk-apb-watchdog-test'] : []) + \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] :
[]) + \
+ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
['arm-cpu-features',
'microbit-test',
--
2.30.1