[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 06/55] target/arm: Implement MVE LCTP
From: |
Peter Maydell |
Subject: |
[PATCH 06/55] target/arm: Implement MVE LCTP |
Date: |
Mon, 7 Jun 2021 17:57:32 +0100 |
Implement the MVE LCTP instruction.
We put its decode and implementation with the other
low-overhead-branch insns because although it is only present if MVE
is implemented it is logically in the same group as the other LOB
insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/t32.decode | 2 ++
target/arm/translate.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 8b2c487fa7a..087e514e0ac 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -674,5 +674,7 @@ BL 1111 0. .......... 11.1 ............
@branch24
DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm
LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
+
+ LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
]
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1a7a32c1be4..2f6c012f672 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8192,6 +8192,30 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
return true;
}
+static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
+{
+ /*
+ * M-profile Loop Clear with Tail Predication. Since our implementation
+ * doesn't cache branch information, all we need to do is reset
+ * FPSCR.LTPSIZE to 4.
+ */
+ TCGv_i32 ltpsize;
+
+ if (!dc_isar_feature(aa32_lob, s) ||
+ !dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ ltpsize = tcg_const_i32(4);
+ store_cpu_field(ltpsize, v7m.ltpsize);
+ return true;
+}
+
+
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
{
TCGv_i32 addr, tmp;
--
2.20.1
- Re: [PATCH 02/55] target/arm: Enable FPSCR.QC bit for MVE, (continued)
- [PATCH 06/55] target/arm: Implement MVE LCTP,
Peter Maydell <=
- [PATCH 08/55] target/arm: Implement MVE DLSTP, Peter Maydell, 2021/06/07
- [PATCH 07/55] target/arm: Implement MVE WLSTP insn, Peter Maydell, 2021/06/07
- [PATCH 09/55] target/arm: Implement MVE LETP insn, Peter Maydell, 2021/06/07
- [PATCH 10/55] target/arm: Add framework for MVE decode, Peter Maydell, 2021/06/07
- [PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/07