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Re: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening form
From: |
Richard Henderson |
Subject: |
Re: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms) |
Date: |
Wed, 9 Jun 2021 10:09:29 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 |
On 6/9/21 3:01 AM, Peter Maydell wrote:
Is the spec forward looking to more than 7 Q registers?
It's tempting to just drop the D:Qd from the decode...
I don't know, but looking at the decode it certainly seems
like the door is being left open to Q8..Q15. Other signs of
this include the existence of the VFPSmallRegisterBank()
function and the way that VLLDM and VLSTM have T2 encodings
whose only difference from the T1 encodings is that you can
specify registers up to D31. Decoding D:Qd and then doing the
range check seemed more in line with the spirit of this...
I agree. We should leave the decode in place.
Do you think it's worthwhile adding a single hook for the register range check
now? E.g.
if (!mve_check_qreg_bank(s, a->qd | a->qn | a->qm)) {
return false;
}
static bool mve_check_qreg_bank(DisasContext *s, int qmask)
{
/*
* See VFPSmallRegisterBank, always true for armv8.1-m.
* So only Q0...Q7 are supported.
*/
return qmask < 8;
}
And, as needed, another one for dregs.
r~
- [PATCH 09/55] target/arm: Implement MVE LETP insn, (continued)
- [PATCH 15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations, Peter Maydell, 2021/06/07
- [PATCH 14/55] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/07
- [PATCH 16/55] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/07
- [PATCH 13/55] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/07