[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 08/57] target/arm: Implement MVE DLSTP
From: |
Peter Maydell |
Subject: |
[PATCH v2 08/57] target/arm: Implement MVE DLSTP |
Date: |
Mon, 14 Jun 2021 16:09:18 +0100 |
Implement the MVE DLSTP insn; this is like the existing DLS
insn, except that it must do an FPU access check and it
sets LTPSIZE to the value specified in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/t32.decode | 9 ++++++---
target/arm/translate.c | 23 +++++++++++++++++++++--
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 6906829265f..1b75db50658 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -671,14 +671,17 @@ BL 1111 0. .......... 11.1 ............
@branch24
# LE and WLS immediate
%lob_imm 1:10 11:1 !function=times_2
- DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
+ DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=4
WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm
size=4
{
LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
# This is WLSTP
WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=%lob_imm
}
-
- LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
+ {
+ LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
+ # This is DLSTP
+ DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001
+ }
]
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 78878e9b194..1ad0e61fac6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8114,13 +8114,32 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a)
return false;
}
if (a->rn == 13 || a->rn == 15) {
- /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */
+ /*
+ * For DLSTP rn == 15 is a related encoding (LCTP); the
+ * other cases caught by this condition are all
+ * CONSTRAINED UNPREDICTABLE: we choose to UNDEF
+ */
return false;
}
- /* Not a while loop, no tail predication: just set LR to the count */
+ if (a->size != 4) {
+ /* DLSTP */
+ if (!dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+ }
+
+ /* Not a while loop: set LR to the count, and set LTPSIZE for DLSTP */
tmp = load_reg(s, a->rn);
store_reg(s, 14, tmp);
+ if (a->size != 4) {
+ /* DLSTP: set FPSCR.LTPSIZE */
+ tmp = tcg_const_i32(a->size);
+ store_cpu_field(tmp, v7m.ltpsize);
+ }
return true;
}
--
2.20.1
- [PATCH v2 00/57] target/arm: First slice of MVE implementation, Peter Maydell, 2021/06/14
- [PATCH v2 02/57] target/arm: Enable FPSCR.QC bit for MVE, Peter Maydell, 2021/06/14
- [PATCH v2 03/57] target/arm: Handle VPR semantics in existing code, Peter Maydell, 2021/06/14
- [PATCH v2 01/57] target/arm: Provide and use H8 and H1_8 macros, Peter Maydell, 2021/06/14
- [PATCH v2 04/57] target/arm: Add handling for PSR.ECI/ICI, Peter Maydell, 2021/06/14
- [PATCH v2 06/57] target/arm: Implement MVE LCTP, Peter Maydell, 2021/06/14
- [PATCH v2 07/57] target/arm: Implement MVE WLSTP insn, Peter Maydell, 2021/06/14
- [PATCH v2 05/57] target/arm: Let vfp_access_check() handle late NOCP checks, Peter Maydell, 2021/06/14
- [PATCH v2 08/57] target/arm: Implement MVE DLSTP,
Peter Maydell <=
- [PATCH v2 09/57] target/arm: Implement MVE LETP insn, Peter Maydell, 2021/06/14
- [PATCH v2 10/57] target/arm: Add framework for MVE decode, Peter Maydell, 2021/06/14
- [PATCH v2 11/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/14
- [PATCH v2 12/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/14
- [PATCH v2 16/57] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations, Peter Maydell, 2021/06/14
- [PATCH v2 17/57] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/14
- [PATCH v2 15/57] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/14