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[PATCH v3 06/44] target/arm: Implement MVE VMVN (register)
From: |
Peter Maydell |
Subject: |
[PATCH v3 06/44] target/arm: Implement MVE VMVN (register) |
Date: |
Thu, 17 Jun 2021 13:15:50 +0100 |
Implement the MVE VMVN(register) operation. Note that for
predication this operation is byte-by-byte.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 2 ++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 4 ++++
target/arm/translate-mve.c | 5 +++++
4 files changed, 14 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 4c89387587d..f1dc52f7a50 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env,
ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 16ee511a5cb..ff8afb682fb 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -30,6 +30,7 @@
@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
+@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0
# Vector loads and stores
@@ -74,3 +75,5 @@ VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ...
0 @1op
VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op
VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op
VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op
+
+VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index e0bb4755748..97da43fa3d6 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -292,3 +292,7 @@ DO_1OP(vrev32h, 4, uint32_t, hswap32)
DO_1OP(vrev64b, 8, uint64_t, bswap64)
DO_1OP(vrev64h, 8, uint64_t, hswap64)
DO_1OP(vrev64w, 8, uint64_t, wswap64)
+
+#define DO_NOT(N) (~(N))
+
+DO_1OP(vmvn, 8, uint64_t, DO_NOT)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 32a8324c5e6..bd908abcff7 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -232,3 +232,8 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a)
};
return do_1op(s, a, fns[a->size]);
}
+
+static bool trans_VMVN(DisasContext *s, arg_1op *a)
+{
+ return do_1op(s, a, gen_helper_mve_vmvn);
+}
--
2.20.1
- [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, (continued)
- [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/17
- [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/17
- [PATCH v3 03/44] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/17
- [PATCH v3 04/44] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/17
- [PATCH v3 06/44] target/arm: Implement MVE VMVN (register),
Peter Maydell <=
- [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/17
- [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/17
- [PATCH v3 08/44] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/17
- [PATCH v3 07/44] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/17
- [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/17
- [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/17
- [PATCH v3 10/44] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/17
- [PATCH v3 14/44] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/17
- [PATCH v3 13/44] target/arm: Implement MVE VMULH, Peter Maydell, 2021/06/17
- [PATCH v3 17/44] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/17