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[PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV
From: |
Peter Maydell |
Subject: |
[PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV |
Date: |
Thu, 17 Jun 2021 13:16:04 +0100 |
Implement the MVE insn VMLSLDAV, which multiplies source elements,
alternately adding and subtracting them, and accumulates into a
64-bit result in a pair of general purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 5 +++++
target/arm/mve.decode | 2 ++
target/arm/mve_helper.c | 5 +++++
target/arm/translate-mve.c | 11 +++++++++++
4 files changed, 23 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 0138e28278a..7356385d60c 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -152,3 +152,8 @@ DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64,
env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vmlsldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlsldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlsldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
+DEF_HELPER_FLAGS_4(mve_vmlsldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index bde54d05bb9..1be2d6b270f 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -145,3 +145,5 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1
0000 @vdup size=2
qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav
VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
+
+VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 0c8bf9232d6..618f0e66d1d 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -537,3 +537,8 @@ DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=)
DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=)
DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=)
+
+DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=)
+DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=)
+DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
+DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index f8ceeac5a4f..77b461c2186 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -461,3 +461,14 @@ static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav
*a)
};
return do_long_dual_acc(s, a, fns[a->size][a->x]);
}
+
+static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
+{
+ static MVEGenDualAccOpFn * const fns[4][2] = {
+ { NULL, NULL },
+ { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh },
+ { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw },
+ { NULL, NULL },
+ };
+ return do_long_dual_acc(s, a, fns[a->size][a->x]);
+}
--
2.20.1
- [PATCH v3 07/44] target/arm: Implement MVE VABS, (continued)
- [PATCH v3 07/44] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/17
- [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/17
- [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/17
- [PATCH v3 10/44] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/17
- [PATCH v3 14/44] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/17
- [PATCH v3 13/44] target/arm: Implement MVE VMULH, Peter Maydell, 2021/06/17
- [PATCH v3 17/44] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/17
- [PATCH v3 15/44] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/17
- [PATCH v3 18/44] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/17
- [PATCH v3 16/44] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/17
- [PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV,
Peter Maydell <=
- [PATCH v3 19/44] target/arm: Implement MVE VMLALDAV, Peter Maydell, 2021/06/17
- [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 28/44] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 25/44] target/arm: Implement MVE VBRSR, Peter Maydell, 2021/06/17
- [PATCH v3 26/44] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/17
- [PATCH v3 27/44] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/17
- [PATCH v3 21/44] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/17
- [PATCH v3 24/44] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 30/44] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/17