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Re: [PATCH for-6.2 21/34] target/arm: Implement MVE VABAV
From: |
Peter Maydell |
Subject: |
Re: [PATCH for-6.2 21/34] target/arm: Implement MVE VABAV |
Date: |
Sat, 17 Jul 2021 23:13:10 +0100 |
On Sat, 17 Jul 2021 at 21:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/13/21 6:37 AM, Peter Maydell wrote:
> > +#define DO_VABAV(OP, ESIZE, TYPE) \
> > + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
> > + void *vm, uint32_t ra) \
> > + { \
> > + uint16_t mask = mve_element_mask(env); \
> > + unsigned e; \
> > + TYPE *m = vm, *n = vn; \
> > + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
> > + if (mask & 1) { \
> > + int64_t n0 = n[H##ESIZE(e)]; \
> > + int64_t m0 = m[H##ESIZE(e)]; \
> > + uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \
>
> Any particular reason you're not using TYPE for n0 and m0?
I wanted to definitely be doing the subtraction with a signed
type wider than the inputs, because that's the way the
pseudocode effectively deals with it, and I didn't feel like
thinking through whether using the smaller and possibly
unsigned types would DTRT :-)
-- PMM
[PATCH for-6.2 34/34] target/arm: Implement MVE interleaving loads/stores, Peter Maydell, 2021/07/13
[PATCH for-6.2 29/34] target/arm: Implement MVE VMOV to/from 2 general-purpose registers, Peter Maydell, 2021/07/13
[PATCH for-6.2 31/34] target/arm: Implement MVE VCTP, Peter Maydell, 2021/07/13
[PATCH for-6.2 32/34] target/arm: Implement MVE scatter-gather insns, Peter Maydell, 2021/07/13