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[PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps
From: |
Peter Maydell |
Subject: |
[PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps |
Date: |
Thu, 29 Jul 2021 12:14:21 +0100 |
Include the MVE VPR register value in the CPU dumps produced by
arm_cpu_dump_state() if we are printing FPU information. This
makes it easier to interpret debug logs when predication is
active.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2866dd76588..a82e39dd97f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1017,6 +1017,9 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
i, v);
}
qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
+ if (cpu_isar_feature(aa32_mve, cpu)) {
+ qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
+ }
}
}
--
2.20.1
- [PATCH for-6.2 00/53] target/arm: MVE slices 3 and 4, Peter Maydell, 2021/07/29
- [PATCH for-6.2 02/53] target/arm: Print MVE VPR in CPU dumps,
Peter Maydell <=
- [PATCH for-6.2 03/53] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>, Peter Maydell, 2021/07/29
- [PATCH for-6.2 04/53] target/arm: Fix signed VADDV, Peter Maydell, 2021/07/29
- [PATCH for-6.2 01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL, Peter Maydell, 2021/07/29
- [PATCH for-6.2 05/53] target/arm: Fix mask handling for MVE narrowing operations, Peter Maydell, 2021/07/29
- [PATCH for-6.2 09/53] target/arm: Factor out mve_eci_mask(), Peter Maydell, 2021/07/29
- [PATCH for-6.2 06/53] target/arm: Fix 48-bit saturating shifts, Peter Maydell, 2021/07/29
- [PATCH for-6.2 08/53] target/arm: Fix calculation of LTP mask when LR is 0, Peter Maydell, 2021/07/29
- [PATCH for-6.2 10/53] target/arm: Fix VPT advance when ECI is non-zero, Peter Maydell, 2021/07/29