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[PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2
From: |
Richard Henderson |
Subject: |
[PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2 |
Date: |
Mon, 11 Apr 2022 17:33:04 -0700 |
This register is present for either VHE or Debugv8p2, and is
RES0 from EL3 when EL2 is not present. Move the definition
out of vhe_reginfo and provide a fallback for missing EL2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7d14650615..210c139818 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7443,11 +7443,20 @@ static const ARMCPRegInfo jazelle_regs[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo contextidr_el2 = {
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
+static const ARMCPRegInfo contextidr_no_el2 = {
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0
+};
+
static const ARMCPRegInfo vhe_reginfo[] = {
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
- .access = PL2_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
@@ -8443,6 +8452,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
+ if (cpu_isar_feature(aa64_vh, cpu) ||
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
+ } else {
+ define_one_arm_cp_reg(cpu, &contextidr_no_el2);
+ }
+ }
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo);
}
--
2.25.1
- [PATCH v2 00/24] target/arm: 8 new features, A76 and N1, Richard Henderson, 2022/04/11
- [PATCH v2 01/24] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/04/11
- [PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2,
Richard Henderson <=
- [PATCH v2 03/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/04/11
- [PATCH v2 04/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/11
- [PATCH v2 08/24] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/11
- [PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS, Richard Henderson, 2022/04/11
- [PATCH v2 17/24] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 19/24] target/arm: Update ISAR fields for ARMv8.8, Richard Henderson, 2022/04/11
- [PATCH v2 10/24] target/arm: Enable FEAT_Debugv8p4 for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 16/24] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 14/24] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/11
- [PATCH v2 18/24] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/11