Re: [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus

[Peter Maydell]

On Sun, 17 Apr 2022 at 18:45, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Supercedes: 20220412003326.588530-1-richard.henderson@linaro.org
> ("target/arm: 8 new features, A76 and N1")
>
> Changes for v3:
>   * More field updates for H.a.  This is not nearly complete, but what
>     I've encountered so far as I've begun implementing SME.
>   * Use bool instead of uint32_t for env->{aarch64,thumb}.
>     I had anticipated other changes for implementing PSTATE.{SM,FA},
>     but dropped those; these seemed like worth keeping.
>   * Use tcg_constant_* more -- got stuck on this while working on...
>   * Lots of cleanups to ARMCPRegInfo.
>   * Discard unreachable cpregs when ELx not available.
>   * Transform EL2 regs to RES0 when EL3 present but EL2 isn't.
>     This greatly simplifies registration of cpregs for new features.
>     Changes contextidr_el2, minimal_ras_reginfo, scxtnum_reginfo
>     within this patch set; other uses coming for SME.

To help reduce the size of this patchset for v4, I've taken most
of the first third into target-arm.next. More specifically, I've
taken patches 2-12, 14-16, 18-20, and 22, making the minor tweaks
noted in code review for patches 7, 14 and 18. Patch 1 is already
upstream. Put another way, I have not taken:

>   target/arm: Use tcg_constant in translate-a64.c
>   target/arm: Use tcg_constant in translate.c
>   target/arm: Use tcg_constant in translate-sve.c

or any of the patches from here on:
>   target/arm: Split out cpregs.h

(I'm still planning to review the second half of this v3.)

thanks
-- PMM