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Re: [PATCH v3 28/51] target/arm: Implement SME LDR, STR
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 28/51] target/arm: Implement SME LDR, STR |
Date: |
Thu, 23 Jun 2022 12:46:56 +0100 |
On Mon, 20 Jun 2022 at 19:24, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We can reuse the SVE functions for LDR and STR, passing in the
> base of the ZA vector and a zero offset.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sme.decode | 7 +++++++
> target/arm/translate-sme.c | 23 +++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v3 17/51] target/arm: Add cpu properties for SME, (continued)
- [PATCH v3 19/51] target/arm: Add SVL to TB flags, Richard Henderson, 2022/06/20
- [PATCH v3 20/51] target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h, Richard Henderson, 2022/06/20
- [PATCH v3 18/51] target/arm: Introduce sve_vqm1_for_el_sm, Richard Henderson, 2022/06/20
- [PATCH v3 22/51] target/arm: Trap AdvSIMD usage when Streaming SVE is active, Richard Henderson, 2022/06/20
[PATCH v3 28/51] target/arm: Implement SME LDR, STR, Richard Henderson, 2022/06/20
- Re: [PATCH v3 28/51] target/arm: Implement SME LDR, STR,
Peter Maydell <=
[PATCH v3 29/51] target/arm: Implement SME ADDHA, ADDVA, Richard Henderson, 2022/06/20
[PATCH v3 30/51] target/arm: Implement FMOPA, FMOPS (non-widening), Richard Henderson, 2022/06/20
[PATCH v3 38/51] target/arm: Enable SME for -cpu max, Richard Henderson, 2022/06/20
[PATCH v3 21/51] target/arm: Add infrastructure for disas_sme, Richard Henderson, 2022/06/20
[PATCH v3 23/51] target/arm: Implement SME RDSVL, ADDSVL, ADDSPL, Richard Henderson, 2022/06/20