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[PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate
From: |
Richard Henderson |
Subject: |
[PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate |
Date: |
Mon, 22 Aug 2022 08:27:04 -0700 |
For page walking, we may require HCR for a security state
that is not "current".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 20 +++++++++++++-------
target/arm/helper.c | 11 ++++++++---
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cea2121f67..a08e546de4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2401,15 +2401,15 @@ static inline bool arm_is_secure(CPUARMState *env)
* Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
* This corresponds to the pseudocode EL2Enabled()
*/
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+{
+ return (arm_feature(env, ARM_FEATURE_EL2)
+ && (!secure || (env->cp15.scr_el3 & SCR_EEL2)));
+}
+
static inline bool arm_is_el2_enabled(CPUARMState *env)
{
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- if (arm_is_secure_below_el3(env)) {
- return (env->cp15.scr_el3 & SCR_EEL2) != 0;
- }
- return true;
- }
- return false;
+ return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
}
#else
@@ -2423,6 +2423,11 @@ static inline bool arm_is_secure(CPUARMState *env)
return false;
}
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+{
+ return false;
+}
+
static inline bool arm_is_el2_enabled(CPUARMState *env)
{
return false;
@@ -2435,6 +2440,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
* "for all purposes other than a direct read or write access of HCR_EL2."
* Not included here is HCR_RW.
*/
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
uint64_t arm_hcr_el2_eff(CPUARMState *env);
uint64_t arm_hcrx_el2_eff(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b9f1a3d826..55355197b8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5101,15 +5101,15 @@ static void hcr_writelow(CPUARMState *env, const
ARMCPRegInfo *ri,
}
/*
- * Return the effective value of HCR_EL2.
+ * Return the effective value of HCR_EL2, at the given security state.
* Bits that are not included here:
* RW (read from SCR_EL3.RW as needed)
*/
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
{
uint64_t ret = env->cp15.hcr_el2;
- if (!arm_is_el2_enabled(env)) {
+ if (!arm_is_el2_enabled_secstate(env, secure)) {
/*
* "This register has no effect if EL2 is not enabled in the
* current Security state". This is ARMv8.4-SecEL2 speak for
@@ -5168,6 +5168,11 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
return ret;
}
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
+{
+ return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
+}
+
/*
* Corresponds to ARM pseudocode function ELIsInHost().
*/
--
2.34.1
- [PATCH v2 20/66] target/arm: Add is_secure parameter to get_phys_addr_pmsav5, (continued)
- [PATCH v2 20/66] target/arm: Add is_secure parameter to get_phys_addr_pmsav5, Richard Henderson, 2022/08/22
- [PATCH v2 19/66] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 21/66] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/08/22
- [PATCH v2 23/66] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/08/22
- [PATCH v2 24/66] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/08/22
- [PATCH v2 22/66] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/08/22
- [PATCH v2 25/66] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/08/22
- [PATCH v2 28/66] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/08/22
- [PATCH v2 27/66] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 26/66] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/08/22
- [PATCH v2 29/66] target/arm: Introduce arm_hcr_el2_eff_secstate,
Richard Henderson <=
- [PATCH v2 31/66] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 32/66] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/08/22
- [PATCH v2 33/66] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/08/22
- [PATCH v2 30/66] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/08/22
- [PATCH v2 34/66] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/08/22
- [PATCH v2 36/66] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/08/22
- [PATCH v2 38/66] accel/tcg: Drop addr member from SavedIOTLB, Richard Henderson, 2022/08/22
- [PATCH v2 39/66] accel/tcg: Suppress auto-invalidate in probe_access_internal, Richard Henderson, 2022/08/22
- [PATCH v2 37/66] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull, Richard Henderson, 2022/08/22
- [PATCH v2 35/66] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/08/22