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Re: [PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw |
Date: |
Fri, 7 Oct 2022 11:42:14 +0100 |
On Sat, 1 Oct 2022 at 18:04, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We had only been reporting the stage2 page size. This causes
> problems if stage1 is using a larger page size (16k, 2M, etc),
> but stage2 is using a smaller page size, because cputlb does
> not set large_page_{addr,mask} properly.
>
> Fix by using the max of the two page sizes.
>
> Reported-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH v3 38/42] target/arm: Fix fault reporting in get_phys_addr_lpae, (continued)
[PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw, Richard Henderson, 2022/10/01
- Re: [PATCH v3 42/42] target/arm: Use the max page size in a 2-stage ptw,
Peter Maydell <=
[PATCH v3 40/42] target/arm: Consider GP an attribute in get_phys_addr_lpae, Richard Henderson, 2022/10/01
Re: [PATCH v3 00/42] target/arm: Implement FEAT_HAFDBS, Peter Maydell, 2022/10/10