Re: [PATCH 1/9] hw/watchdog/wdt_aspeed: Map the whole MMIO range

[Cédric Le Goater]

On 12/29/22 16:23, Philippe Mathieu-Daudé wrote:
> Avoid confusing two different things:
> - the WDT I/O region size ('iosize')
> - at which offset the SoC map the WDT ('offset')
> While it is often the same, we can map smaller region sizes at
> larger offsets.
>
> Here we are interested in the I/O region size. Rename as 'iosize'
> and map the whole range, not only the first implemented registers.
> Unimplemented registers accesses are already logged as guest-errors.
>
> Otherwise when booting the demo in [*] we get:
>
>    aspeed.io: unimplemented device write (size 4, offset 0x1851a8, value 
> 0x030f1ff1)
>    aspeed.io: unimplemented device write (size 4, offset 0x1851ac, value 
> 0x03fffff1)
>    aspeed.io: unimplemented device write (size 4, offset 0x185128, value 
> 0x030f1ff1)
>    aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 
> 0x03fffff1)

These are unimplemented registers related to software mode reset, which is a new
feature of the AST2600 SoC. The AST10x0 SoCs add a few more regs, hence the 
larger
MMIO width for the WDT registers. Until now, they have been harmless.

> [*] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/arm/aspeed_ast10x0.c          |  2 +-
>   hw/arm/aspeed_ast2600.c          |  2 +-
>   hw/arm/aspeed_soc.c              |  2 +-
>   hw/watchdog/wdt_aspeed.c         | 12 +++++++-----
>   include/hw/watchdog/wdt_aspeed.h |  2 +-
>   5 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 4d0b9b115f..122b3fd3f3 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -325,7 +325,7 @@ static void aspeed_soc_ast1030_realize(DeviceState 
> *dev_soc, Error **errp)
>               return;
>           }
>           aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
> -                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
> +                        sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize);
>       }
>   
>       /* GPIO */
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index cd75465c2b..a79e05ddbd 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -472,7 +472,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, 
> Error **errp)
>               return;
>           }
>           aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
> -                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
> +                        sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize);
>       }
>   
>       /* RAM */
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index b05b9dd416..2c0924d311 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -393,7 +393,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error 
> **errp)
>               return;
>           }
>           aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
> -                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
> +                        sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize);
>       }
>   
>       /* RAM  */
> diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
> index d753693a2e..c1311ce74c 100644
> --- a/hw/watchdog/wdt_aspeed.c
> +++ b/hw/watchdog/wdt_aspeed.c
> @@ -260,6 +260,7 @@ static void aspeed_wdt_realize(DeviceState *dev, Error 
> **errp)
>   {
>       SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>       AspeedWDTState *s = ASPEED_WDT(dev);
> +    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
>   
>       assert(s->scu);
>   
> @@ -270,8 +271,9 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
>        */
>       s->pclk_freq = PCLK_HZ;
>   
> +    assert(awc->iosize >= ASPEED_WDT_REGS_MAX * 4);
>       memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
> -                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
> +                          TYPE_ASPEED_WDT, awc->iosize);
>       sysbus_init_mmio(sbd, &s->iomem);
>   }
>   
> @@ -309,7 +311,7 @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
>       AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
>   
>       dc->desc = "ASPEED 2400 Watchdog Controller";
> -    awc->offset = 0x20;
> +    awc->iosize = 0x20;
>       awc->ext_pulse_width_mask = 0xff;
>       awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
>       awc->wdt_reload = aspeed_wdt_reload;
> @@ -346,7 +348,7 @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, 
> void *data)
>       AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
>   
>       dc->desc = "ASPEED 2500 Watchdog Controller";
> -    awc->offset = 0x20;
> +    awc->iosize = 0x20;
>       awc->ext_pulse_width_mask = 0xfffff;
>       awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
>       awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
> @@ -369,7 +371,7 @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, 
> void *data)
>       AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
>   
>       dc->desc = "ASPEED 2600 Watchdog Controller";
> -    awc->offset = 0x40;
> +    awc->iosize = 0x40;
>       awc->ext_pulse_width_mask = 0xfffff; /* TODO */
>       awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
>       awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
> @@ -392,7 +394,7 @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, 
> void *data)
>       AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
>   
>       dc->desc = "ASPEED 1030 Watchdog Controller";
> -    awc->offset = 0x80;
> +    awc->iosize = 0x80;
>       awc->ext_pulse_width_mask = 0xfffff; /* TODO */
>       awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
>       awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
> diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
> index dfa5dfa424..db91ee6b51 100644
> --- a/include/hw/watchdog/wdt_aspeed.h
> +++ b/include/hw/watchdog/wdt_aspeed.h
> @@ -40,7 +40,7 @@ struct AspeedWDTState {
>   struct AspeedWDTClass {
>       SysBusDeviceClass parent_class;
>   
> -    uint32_t offset;
> +    uint32_t iosize;
>       uint32_t ext_pulse_width_mask;
>       uint32_t reset_ctrl_reg;
>       void (*reset_pulse)(AspeedWDTState *s, uint32_t property);