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[PATCH qemu v2 3/3] target/arm/gdbstub: Support reading M security exten
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From: |
~dreiss-meta |
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Subject: |
[PATCH qemu v2 3/3] target/arm/gdbstub: Support reading M security extension registers from GDB |
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Date: |
Mon, 09 Jan 2023 15:05:24 -0800 |
From: David Reiss <dreiss@meta.com>
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss <dreiss@meta.com>
---
target/arm/cpu.h | 15 +++++-
target/arm/gdbstub.c | 116 ++++++++++++++++++++++++++++++++++++++++++
target/arm/m_helper.c | 23 ++++-----
3 files changed, 139 insertions(+), 15 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fdbb0d9107..661ca832bf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -857,6 +857,7 @@ struct ArchCPU {
DynamicGDBXMLInfo dyn_sysreg_xml;
DynamicGDBXMLInfo dyn_svereg_xml;
DynamicGDBXMLInfo dyn_m_systemreg_xml;
+ DynamicGDBXMLInfo dyn_m_securereg_xml;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
@@ -1102,12 +1103,13 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t
*buf, int reg);
/*
* Helpers to dynamically generate XML descriptions of the sysregs,
- * SVE registers, and M-profile system registers.
+ * SVE registers, M-profile system, and M-profile secure extension registers.
* Returns the number of registers in each set.
*/
int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
int arm_gen_dynamic_m_systemreg_xml(CPUState *cpu, int base_reg);
+int arm_gen_dynamic_m_securereg_xml(CPUState *cpu, int base_reg);
/* Returns the dynamically generated XML for the gdb stub.
* Returns a pointer to the XML contents for the specified XML file or NULL
@@ -1607,6 +1609,17 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#endif
}
+/*
+ * Return a pointer to the location where we currently store the
+ * stack pointer for the requested security state and thread mode.
+ * This pointer will become invalid if the CPU state is updated
+ * such that the stack pointers are switched around (eg changing
+ * the SPSEL control bit).
+ */
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+ bool spsel);
+
+
#define HCR_VM (1ULL << 0)
#define HCR_SWIO (1ULL << 1)
#define HCR_PTW (1ULL << 2)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index ae7fe2c800..cbccd4aa2c 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -437,6 +437,110 @@ int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int
base_reg)
return info->num;
}
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+ switch (reg) {
+ case 0: /* MSP_S */
+ return gdb_get_reg32(buf, *arm_v7m_get_sp_ptr(env, true, false, true));
+ case 1: /* PSP_S */
+ return gdb_get_reg32(buf, *arm_v7m_get_sp_ptr(env, true, true, true));
+ case 2: /* MSPLIM_S */
+ return gdb_get_reg32(buf, env->v7m.msplim[M_REG_S]);
+ case 3: /* PSPLIM_S */
+ return gdb_get_reg32(buf, env->v7m.psplim[M_REG_S]);
+ case 4: /* PRIMASK_S */
+ return gdb_get_reg32(buf, env->v7m.primask[M_REG_S]);
+ case 5: /* BASEPRI_S */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.basepri[M_REG_S]);
+ case 6: /* FAULTMASK_S */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.faultmask[M_REG_S]);
+ case 7: /* CONTROL_S */
+ return gdb_get_reg32(buf, env->v7m.control[M_REG_S]);
+ case 8: /* MSP_NS */
+ return gdb_get_reg32(buf, *arm_v7m_get_sp_ptr(env, false, false,
true));
+ case 9: /* PSP_NS */
+ return gdb_get_reg32(buf, *arm_v7m_get_sp_ptr(env, false, true, true));
+ case 10: /* MSPLIM_NS */
+ return gdb_get_reg32(buf, env->v7m.msplim[M_REG_NS]);
+ case 11: /* PSPLIM_NS */
+ return gdb_get_reg32(buf, env->v7m.psplim[M_REG_NS]);
+ case 12: /* PRIMASK_NS */
+ return gdb_get_reg32(buf, env->v7m.primask[M_REG_NS]);
+ case 13: /* BASEPRI_NS */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.basepri[M_REG_NS]);
+ case 14: /* FAULTMASK_NS */
+ if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
+ return 0;
+ }
+ return gdb_get_reg32(buf, env->v7m.faultmask[M_REG_NS]);
+ case 15: /* CONTROL_NS */
+ return gdb_get_reg32(buf, env->v7m.control[M_REG_NS]);
+ }
+
+ return 0;
+}
+
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+ /* TODO: Implement. */
+ return 0;
+}
+
+int arm_gen_dynamic_m_securereg_xml(CPUState *cs, int base_reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ GString *s = g_string_new(NULL);
+ DynamicGDBXMLInfo *info = &cpu->dyn_m_securereg_xml;
+ bool is_main = arm_feature(env, ARM_FEATURE_M_MAIN);
+
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
+
+ g_autoptr(GArray) regs = g_array_new(false, true, sizeof(const char *));
+ /* 0 */ g_array_append_str_literal(regs, "msp_s");
+ /* 1 */ g_array_append_str_literal(regs, "psp_s");
+ /* 2 */ g_array_append_str_literal(regs, "msplim_s");
+ /* 3 */ g_array_append_str_literal(regs, "psplim_s");
+ /* 4 */ g_array_append_str_literal(regs, "primask_s");
+ /* 5 */ g_array_append_str_literal(regs, is_main ? "basepri_s" : "");
+ /* 6 */ g_array_append_str_literal(regs, is_main ? "faultmask_s" : "");
+ /* 7 */ g_array_append_str_literal(regs, "control_s");
+ /* 8 */ g_array_append_str_literal(regs, "msp_ns");
+ /* 9 */ g_array_append_str_literal(regs, "psp_ns");
+ /* 10 */ g_array_append_str_literal(regs, "msplim_ns");
+ /* 11 */ g_array_append_str_literal(regs, "psplim_ns");
+ /* 12 */ g_array_append_str_literal(regs, "primask_ns");
+ /* 13 */ g_array_append_str_literal(regs, is_main ? "basepri_ns" : "");
+ /* 14 */ g_array_append_str_literal(regs, is_main ? "faultmask_ns" : "");
+ /* 15 */ g_array_append_str_literal(regs, "control_ns");
+
+ for (int idx = 0; idx < regs->len; idx++) {
+ const char *name = g_array_index(regs, const char *, idx);
+ if (*name != '\0') {
+ g_string_append_printf(s,
+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+ name, base_reg);
+ }
+ base_reg++;
+ }
+ info->num = regs->len;
+
+ g_string_append_printf(s, "</feature>");
+ info->desc = g_string_free(s, false);
+ return info->num;
+}
+
struct TypeSize {
const char *gdb_type;
int size;
@@ -567,6 +671,8 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const
char *xmlname)
return cpu->dyn_svereg_xml.desc;
} else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
return cpu->dyn_m_systemreg_xml.desc;
+ } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
+ return cpu->dyn_m_securereg_xml.desc;
}
return NULL;
}
@@ -618,6 +724,16 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
arm_gen_dynamic_m_systemreg_xml(
cs, cs->gdb_num_regs),
"arm-m-system.xml", 0);
+ if (arm_feature(env, ARM_FEATURE_V8) &&
+ arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+ gdb_register_coprocessor(cs,
+ arm_gdb_get_m_secextreg,
+ arm_gdb_set_m_secextreg,
+ arm_gen_dynamic_m_securereg_xml(
+ cs, cs->gdb_num_regs),
+ "arm-m-secext.xml", 0);
+
+ }
}
}
if (cpu_isar_feature(aa32_mve, cpu)) {
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index e8fbe1599a..a9b27ad060 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -605,15 +605,10 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
arm_rebuild_hflags(env);
}
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
- bool spsel)
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+ bool spsel)
{
/*
- * Return a pointer to the location where we currently store the
- * stack pointer for the requested security state and thread mode.
- * This pointer will become invalid if the CPU state is updated
- * such that the stack pointers are switched around (eg changing
- * the SPSEL control bit).
* Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
* Unlike that pseudocode, we require the caller to pass us in the
* SPSEL control bit value; this is because we also use this
@@ -765,8 +760,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr,
bool dotailchain,
!mode;
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
- frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
- lr & R_V7M_EXCRET_SPSEL_MASK);
+ frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
+ lr & R_V7M_EXCRET_SPSEL_MASK);
want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
if (want_psp) {
limit = env->v7m.psplim[M_REG_S];
@@ -1611,10 +1606,10 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
* use 'frame_sp_p' after we do something that makes it invalid.
*/
bool spsel = env->v7m.control[return_to_secure] &
R_V7M_CONTROL_SPSEL_MASK;
- uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
- return_to_secure,
- !return_to_handler,
- spsel);
+ uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env,
+ return_to_secure,
+ !return_to_handler,
+ spsel);
uint32_t frameptr = *frame_sp_p;
bool pop_ok = true;
ARMMMUIdx mmu_idx;
@@ -1920,7 +1915,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
threadmode = !arm_v7m_is_handler_mode(env);
spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
- frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+ frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
frameptr = *frame_sp_p;
/*
--
2.34.5