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[PATCH 17/23] target/arm: Mark up sysregs for HFGITR bits 12..17
From: |
Peter Maydell |
Subject: |
[PATCH 17/23] target/arm: Mark up sysregs for HFGITR bits 12..17 |
Date: |
Fri, 27 Jan 2023 17:55:01 +0000 |
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 6 ++++++
target/arm/helper.c | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 6596c2a1233..1f74308ef5d 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -660,6 +660,12 @@ typedef enum FGTBit {
DO_BIT(HFGITR, DCCVADP),
DO_BIT(HFGITR, DCCIVAC),
DO_BIT(HFGITR, DCZVA),
+ DO_BIT(HFGITR, ATS1E1R),
+ DO_BIT(HFGITR, ATS1E1W),
+ DO_BIT(HFGITR, ATS1E0R),
+ DO_BIT(HFGITR, ATS1E0W),
+ DO_BIT(HFGITR, ATS1E1RP),
+ DO_BIT(HFGITR, ATS1E1WP),
} FGTBit;
#undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 51866ba70e9..8b9c7fcc3a4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5400,18 +5400,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E1R,
.writefn = ats_write64 },
{ .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E1W,
.writefn = ats_write64 },
{ .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E0R,
.writefn = ats_write64 },
{ .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E0W,
.writefn = ats_write64 },
{ .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
@@ -7880,10 +7884,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
{ .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E1RP,
.writefn = ats_write64 },
{ .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
.access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+ .fgt = FGT_ATS1E1WP,
.writefn = ats_write64 },
};
--
2.34.1
- Re: [PATCH 02/23] target/arm: Correct syndrome for ATS12NSO* at Secure EL1, (continued)
- [PATCH 05/23] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps, Peter Maydell, 2023/01/27
- [PATCH 03/23] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}, Peter Maydell, 2023/01/27
- [PATCH 11/23] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/01/27
- [PATCH 06/23] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1, Peter Maydell, 2023/01/27
- [PATCH 17/23] target/arm: Mark up sysregs for HFGITR bits 12..17,
Peter Maydell <=
- [PATCH 18/23] target/arm: Mark up sysregs for HFGITR bits 18..47, Peter Maydell, 2023/01/27
- [PATCH 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11, Peter Maydell, 2023/01/27
- [PATCH 09/23] target/arm: Implement FGT trapping infrastructure, Peter Maydell, 2023/01/27
- [PATCH 14/23] target/arm: Mark up sysregs for HDFGRTR bits 0..11, Peter Maydell, 2023/01/27
- [PATCH 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/01/27