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[PATCH 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63
From: |
Peter Maydell |
Subject: |
[PATCH 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63 |
Date: |
Fri, 27 Jan 2023 17:55:03 +0000 |
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.
Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
* ERET, ERETAA, ERETAB
* SVC
We will have to handle those separately and manually.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 4 ++++
target/arm/helper.c | 9 +++++++++
2 files changed, 13 insertions(+)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 2e5ac6b4f98..efcf9181b97 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -696,6 +696,10 @@ typedef enum FGTBit {
DO_BIT(HFGITR, TLBIVAAE1),
DO_BIT(HFGITR, TLBIVALE1),
DO_BIT(HFGITR, TLBIVAALE1),
+ DO_BIT(HFGITR, CFPRCTX),
+ DO_BIT(HFGITR, DVPRCTX),
+ DO_BIT(HFGITR, CPPRCTX),
+ DO_BIT(HFGITR, DCCVAC),
} FGTBit;
#undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5b9cc087e28..c0403aadae2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5295,6 +5295,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
+ .fgt = FGT_DCCVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
@@ -7588,10 +7589,12 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
{ .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
.type = ARM_CP_NOP, .access = PL0_W,
+ .fgt = FGT_DCCVAC,
.accessfn = aa64_cacheop_poc_access },
{ .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
@@ -7747,24 +7750,30 @@ static CPAccessResult access_predinv(CPUARMState *env,
const ARMCPRegInfo *ri,
static const ARMCPRegInfo predinv_reginfo[] = {
{ .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
+ .fgt = FGT_CFPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
{ .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
+ .fgt = FGT_DVPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
{ .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
+ .fgt = FGT_CPPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
/*
* Note the AArch32 opcodes have a different OPC1.
*/
{ .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
+ .fgt = FGT_CFPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
{ .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
+ .fgt = FGT_DVPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
{ .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
+ .fgt = FGT_CPPRCTX,
.type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
};
--
2.34.1
- [PATCH 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63, (continued)
- [PATCH 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/01/27
- [PATCH 10/23] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/01/27
- [PATCH 08/23] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/01/27
- [PATCH 12/23] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/01/27
- [PATCH 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled, Peter Maydell, 2023/01/27
- [PATCH 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63,
Peter Maydell <=
- [PATCH 13/23] target/arm: Mark up sysregs for HFGRTR bits 36..63, Peter Maydell, 2023/01/27
- [PATCH 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier, Peter Maydell, 2023/01/27
- [PATCH 20/23] target/arm: Implement the HFGITR_EL2.ERET trap, Peter Maydell, 2023/01/27
- [PATCH 22/23] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps, Peter Maydell, 2023/01/27
- [PATCH 21/23] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps, Peter Maydell, 2023/01/27