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[PATCH v2 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enable
From: |
Peter Maydell |
Subject: |
[PATCH v2 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled |
Date: |
Mon, 30 Jan 2023 18:24:43 +0000 |
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
target/arm/op_helper.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6f6772d8e04..66966869218 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11716,7 +11716,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState
*env, int fp_el,
DP_TBFLAG_A32(flags, VFPEN, 1);
}
- if (el < 2 && env->cp15.hstr_el2 &&
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 7797a137af6..dec03310ad5 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -663,6 +663,7 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env,
uint32_t key,
* we only need to check here for traps from EL0.
*/
if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
+ arm_is_el2_enabled(env) &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
uint32_t mask = 1 << ri->crn;
--
2.34.1
- [PATCH v2 00/23] target/arm: Implement FEAT_FGT fine-grained traps, Peter Maydell, 2023/01/30
- [PATCH v2 01/23] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly, Peter Maydell, 2023/01/30
- [PATCH v2 03/23] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}, Peter Maydell, 2023/01/30
- [PATCH v2 04/23] target/arm: Move do_coproc_insn() syndrome calculation earlier, Peter Maydell, 2023/01/30
- [PATCH v2 05/23] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps, Peter Maydell, 2023/01/30
- [PATCH v2 06/23] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1, Peter Maydell, 2023/01/30
- [PATCH v2 02/23] target/arm: Correct syndrome for ATS12NSO* at Secure EL1, Peter Maydell, 2023/01/30
- [PATCH v2 12/23] target/arm: Mark up sysregs for HFGRTR bits 24..35, Peter Maydell, 2023/01/30
- [PATCH v2 09/23] target/arm: Implement FGT trapping infrastructure, Peter Maydell, 2023/01/30
- [PATCH v2 07/23] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled,
Peter Maydell <=
- [PATCH v2 19/23] target/arm: Mark up sysregs for HFGITR bits 48..63, Peter Maydell, 2023/01/30
- [PATCH v2 20/23] target/arm: Implement the HFGITR_EL2.ERET trap, Peter Maydell, 2023/01/30
- [PATCH v2 10/23] target/arm: Mark up sysregs for HFGRTR bits 0..11, Peter Maydell, 2023/01/30
- [PATCH v2 08/23] target/arm: Define the FEAT_FGT registers, Peter Maydell, 2023/01/30
- [PATCH v2 11/23] target/arm: Mark up sysregs for HFGRTR bits 12..23, Peter Maydell, 2023/01/30
- [PATCH v2 23/23] target/arm: Enable FEAT_FGT on '-cpu max', Peter Maydell, 2023/01/30
- [PATCH v2 14/23] target/arm: Mark up sysregs for HDFGRTR bits 0..11, Peter Maydell, 2023/01/30
- [PATCH v2 13/23] target/arm: Mark up sysregs for HFGRTR bits 36..63, Peter Maydell, 2023/01/30
- [PATCH v2 15/23] target/arm: Mark up sysregs for HDFGRTR bits 12..63, Peter Maydell, 2023/01/30
- [PATCH v2 16/23] target/arm: Mark up sysregs for HFGITR bits 0..11, Peter Maydell, 2023/01/30