[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 2/2] via-ide: Also emulate non 100% native mode

From: Mark Cave-Ayland
Subject: Re: [PATCH 2/2] via-ide: Also emulate non 100% native mode
Date: Thu, 5 Mar 2020 18:40:48 +0000
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0

On 04/03/2020 22:33, BALATON Zoltan wrote:

>>>>>> AFAICT this then only leaves the question: why does the firmware set
>>>>>> PCI_INTERRUPT_LINE to 9, which is presumably why you are seeing problems 
>>>>>> running
>>>>>> MorphOS under QEMU.
>>>>> Linux does try to handle both true native mode and half-native mode. It 
>>>>> only uses
>>>>> half-native mode if finds IRQ14 on Pegasos, otherwise skips Pegasos 
>>>>> specific fixup
>>>>> and uses true native mode setup. I don't know what MorphOS does but I 
>>>>> think it
>>>>> justs
>>>>> knows that Pegasos2 has this quirk and does not look at the device tree 
>>>>> at all.

I just a quick look at the PCI specification and found this interesting 
paragraph in
the section about "Interrupt Line":

"The Interrupt Line register is an eight-bit register used to communicate 
line routing information. The register is read/write and must be implemented by 
device (or device function) that uses an interrupt pin. POST software will 
write the
routing information into this register as it initializes and configures the 

"The value in this register tells which input of the system interrupt 
the device's interrupt pin is connected to. The device itself does not use this
value, rather it is used by device drivers and operating systems. Device 
drivers and
operating systems can use this information to determine priority and vector
information. Values in this register are architecture-specific [43]."

[43] For x86 based PCs, the values in this register correspond to IRQ numbers 
of the standard dual 8259 configuration. The value 255 is defined as meaning
"unknown" or "no connection" to the interrupt controller. Values between 15 and 
are reserved.

The key part here is "The device itself does not use this value, rather it is 
used by
device drivers and operating systems" since this immediately tells us that the
existing code in hw/ide/via.c which uses the interrupt line value for IRQ 
routing is
incorrect and should be removed.

If we do that the next question is how does the VIA know whether the use the PCI
interrupt or the legacy interrupt? Another look at the datasheet showed that 
there is
another possibility: PCI configuration space register 0x3d (Interrupt pin) is
documented as having value 0 == Legacy IRQ routing which should be the initial 
on reset, but QEMU incorrectly sets it to 1 which indicates PCI IRQ routing.

In your previous email you included a trace of the PCI configuration accesses 
to the
via-ide device. Can you try this again with the following diff and post the same
output once again?

diff --git a/hw/ide/via.c b/hw/ide/via.c
index 096de8dba0..db9f4af861 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -139,7 +139,7 @@ static void via_ide_reset(DeviceState *dev)
     pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
     pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
     pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h 
-    pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
+    pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000000e);

     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
     pci_set_long(pci_conf + 0x40, 0x0a090600);



reply via email to

[Prev in Thread] Current Thread [Next in Thread]