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[PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4
From: |
Klaus Jensen |
Subject: |
[PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4 |
Date: |
Tue, 19 Jan 2021 11:14:52 +0100 |
From: Klaus Jensen <k.jensen@samsung.com>
This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with
some more PMR work added (PMR RDS/WDS support).
This includes a resurrection of Andrzej's series[1] from back July.
Andrzej's main patch basically moved the CMB from BAR 2 into an offset
in BAR 4 (located after the MSI-X table and PBA). Having an offset on
the CMB causes a bunch of calculations related to address mapping to
change.
So, since I couldn't get the patch to apply cleanly I took a stab at
implementing the suggestion I originally came up with: simply move the
MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB
boundary after the main NVMe controller registers). This way we can keep
the CMB at offset zero in its own BAR and free up BAR 4 for use by PMR.
This makes the patch simpler and does not impact any of the existing
address mapping code.
[1]:
https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/
Changes for v3
~~~~~~~~~~~~~~
- Fix a masking bug in "hw/block/nvme: fix 64 bit register hi/lo split
writes" (Minwoo)
- Restore a deleted comment in "hw/block/nvme: remove redundant
zeroing of PMR registers" (Minwoo)
- Restore the 'legacy-cmb' parameter from v1 to allow the device to
exhibit the v1.3 CMB behavior.
Changes for v2
~~~~~~~~~~~~~~
- Rebased on nvme-next
- Added a fix for 64 bit register hi/lo split writes
- Added the patches from "hw/block/nvme: cmb enhancements and bump to
v1.4" to the back of this.
- As suggested by Keith, I removed "legacy CMB" support - the patch
now exclusively bumps the support to the "v1.4 variant", so the
linux kernel nvme gang have to get their game on ;)
Andrzej Jakowski (1):
hw/block/nvme: indicate CMB support through controller capabilities
register
Klaus Jensen (9):
hw/block/nvme: add size to mmio read/write trace events
hw/block/nvme: fix 64 bit register hi/lo split writes
hw/block/nvme: move msix table and pba to BAR 0
hw/block/nvme: allow cmb and pmr to coexist
hw/block/nvme: rename PMR/CMB shift/mask fields
hw/block/nvme: remove redundant zeroing of PMR registers
hw/block/nvme: disable PMR at boot up
hw/block/nvme: bump to v1.4
hw/block/nvme: lift cmb restrictions
Naveen Nagar (1):
hw/block/nvme: add PMR RDS/WDS support
Padmakar Kalghatgi (1):
hw/block/nvme: move cmb logic to v1.4
hw/block/nvme.h | 17 +-
include/block/nvme.h | 125 +++++++++++++--
hw/block/nvme.c | 350 +++++++++++++++++++++++++++---------------
hw/block/trace-events | 6 +-
4 files changed, 351 insertions(+), 147 deletions(-)
--
2.30.0
- [PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4,
Klaus Jensen <=
- [PATCH v3 01/12] hw/block/nvme: add size to mmio read/write trace events, Klaus Jensen, 2021/01/19
- [PATCH v3 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes, Klaus Jensen, 2021/01/19
- [PATCH v3 04/12] hw/block/nvme: move msix table and pba to BAR 0, Klaus Jensen, 2021/01/19
- [PATCH v3 03/12] hw/block/nvme: indicate CMB support through controller capabilities register, Klaus Jensen, 2021/01/19
- [PATCH v3 05/12] hw/block/nvme: allow cmb and pmr to coexist, Klaus Jensen, 2021/01/19
- [PATCH v3 06/12] hw/block/nvme: rename PMR/CMB shift/mask fields, Klaus Jensen, 2021/01/19
- [PATCH v3 07/12] hw/block/nvme: remove redundant zeroing of PMR registers, Klaus Jensen, 2021/01/19
- [PATCH v3 08/12] hw/block/nvme: disable PMR at boot up, Klaus Jensen, 2021/01/19
- [PATCH v3 09/12] hw/block/nvme: add PMR RDS/WDS support, Klaus Jensen, 2021/01/19