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[PATCH v3 4/9] hw/block/pflash_cfi02: Attach memory region in boards
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From: |
Bernhard Beschow |
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Subject: |
[PATCH v3 4/9] hw/block/pflash_cfi02: Attach memory region in boards |
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Date: |
Sun, 16 Oct 2022 14:27:32 +0200 |
pflash_cfi02_register() had a parameter which was only passed to
sysbus_mmio_map() but not used otherwise. Pulling out sysbus_mmio_map()
resolves that parameter and concentrates the memory region setup in
board code. Furthermore, it allows attaching cfi02 devices relative to
some parent bus rather than to the global "sysbus".
While at it, replace sysbus_mmio_map() with non-sysbus equivalents.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/arm/digic_boards.c | 16 ++++++++++------
hw/arm/musicpal.c | 15 +++++++++------
hw/arm/xilinx_zynq.c | 12 +++++++-----
hw/block/pflash_cfi02.c | 9 ++++++---
hw/sh4/r2d.c | 11 +++++++----
include/hw/block/flash.h | 4 ++--
6 files changed, 41 insertions(+), 26 deletions(-)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 4093af09cb..d3c5426cf9 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -116,12 +116,16 @@ static void digic4_add_k8p3215uqb_rom(DigicState *s,
hwaddr addr,
#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024)
- pflash_cfi02_register(addr, "pflash", FLASH_K8P3215UQB_SIZE,
- NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
- DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE,
- 4,
- 0x00EC, 0x007E, 0x0003, 0x0001,
- 0x0555, 0x2aa, 0);
+ PFlashCFI02 *pfl;
+
+ pfl = pflash_cfi02_register("pflash", FLASH_K8P3215UQB_SIZE,
+ NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
+ DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE,
+ 4,
+ 0x00EC, 0x007E, 0x0003, 0x0001,
+ 0x0555, 0x2aa, 0);
+ memory_region_add_subregion(get_system_memory(), addr,
+ pflash_cfi02_get_memory(pfl));
digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, filename);
}
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index b65c020115..efad741f6d 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1261,6 +1261,7 @@ static void musicpal_init(MachineState *machine)
/* Register flash */
dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
+ PFlashCFI02 *pfl;
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
flash_size = blk_getlength(blk);
@@ -1275,12 +1276,14 @@ static void musicpal_init(MachineState *machine)
* 0xFF800000 (if there is 8 MB flash). So remap flash access if the
* image is smaller than 32 MB.
*/
- pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
- "musicpal.flash", flash_size,
- blk, 0x10000,
- MP_FLASH_SIZE_MAX / flash_size,
- 2, 0x00BF, 0x236D, 0x0000, 0x0000,
- 0x5555, 0x2AAA, 0);
+ pfl = pflash_cfi02_register("musicpal.flash", flash_size,
+ blk, 0x10000,
+ MP_FLASH_SIZE_MAX / flash_size,
+ 2, 0x00BF, 0x236D, 0x0000, 0x0000,
+ 0x5555, 0x2AAA, 0);
+ memory_region_add_subregion(address_space_mem,
+ 0x100000000ULL - MP_FLASH_SIZE_MAX,
+ pflash_cfi02_get_memory(pfl));
}
sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3190cc0b8d..a2abb1cf31 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -182,6 +182,7 @@ static void zynq_init(MachineState *machine)
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev, *slcr;
SysBusDevice *busdev;
+ PFlashCFI02 *pfl;
qemu_irq pic[64];
int n;
@@ -218,11 +219,12 @@ static void zynq_init(MachineState *machine)
DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
/* AMD */
- pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- FLASH_SECTOR_SIZE, 1,
- 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
- 0);
+ pfl = pflash_cfi02_register("zynq.pflash", FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ FLASH_SECTOR_SIZE, 1, 1, 0x0066, 0x0022,
0x0000,
+ 0x0000, 0x0555, 0x2aa, 0);
+ memory_region_add_subregion(address_space_mem, 0xe2000000,
+ pflash_cfi02_get_memory(pfl));
/* Create the main clock source, and feed slcr with it */
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index ff2fe154c1..60039e0d52 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -999,8 +999,7 @@ static void pflash_cfi02_register_types(void)
type_init(pflash_cfi02_register_types)
-PFlashCFI02 *pflash_cfi02_register(hwaddr base,
- const char *name,
+PFlashCFI02 *pflash_cfi02_register(const char *name,
hwaddr size,
BlockBackend *blk,
uint32_t sector_len,
@@ -1031,6 +1030,10 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base,
qdev_prop_set_string(dev, "name", name);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI02(dev);
}
+
+MemoryRegion *pflash_cfi02_get_memory(PFlashCFI02 *fl)
+{
+ return sysbus_mmio_get_region(SYS_BUS_DEVICE(fl), 0);
+}
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 39fc4f19d9..0af8f0e137 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -239,6 +239,7 @@ static void r2d_init(MachineState *machine)
MemoryRegion *sdram = g_new(MemoryRegion, 1);
qemu_irq *irq;
DriveInfo *dinfo;
+ PFlashCFI02 *pfl;
int i;
DeviceState *dev;
SysBusDevice *busdev;
@@ -302,10 +303,12 @@ static void r2d_init(MachineState *machine)
* addressable in words of 16bit.
*/
dinfo = drive_get(IF_PFLASH, 0, 0);
- pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
- 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
- 0x555, 0x2aa, 0);
+ pfl = pflash_cfi02_register("r2d.flash", FLASH_SIZE,
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+ 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
+ 0x555, 0x2aa, 0);
+ memory_region_add_subregion(get_system_memory(), 0x0,
+ pflash_cfi02_get_memory(pfl));
/* NIC: rtl8139 on-board, and 2 slots. */
for (i = 0; i < nb_nics; i++)
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
index 5f9ba18de1..52d6bcd56a 100644
--- a/include/hw/block/flash.h
+++ b/include/hw/block/flash.h
@@ -30,8 +30,7 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo
*dinfo);
OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02)
-PFlashCFI02 *pflash_cfi02_register(hwaddr base,
- const char *name,
+PFlashCFI02 *pflash_cfi02_register(const char *name,
hwaddr size,
BlockBackend *blk,
uint32_t sector_len,
@@ -42,6 +41,7 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base,
uint16_t unlock_addr0,
uint16_t unlock_addr1,
int be);
+MemoryRegion *pflash_cfi02_get_memory(PFlashCFI02 *fl);
/* nand.c */
DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
--
2.38.0
- [PATCH v3 0/9] ppc/e500: Add support for two types of flash, cleanup, Bernhard Beschow, 2022/10/16
- [PATCH v3 1/9] hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two, Bernhard Beschow, 2022/10/16
- [PATCH v3 2/9] hw/{arm,ppc}: Resolve unreachable code, Bernhard Beschow, 2022/10/16
- [PATCH v3 3/9] hw/block/pflash_cfi01: Attach memory region in boards, Bernhard Beschow, 2022/10/16
- [PATCH v3 4/9] hw/block/pflash_cfi02: Attach memory region in boards,
Bernhard Beschow <=
- [PATCH v3 5/9] hw/sd/sdhci-internal: Unexport ESDHC defines, Bernhard Beschow, 2022/10/16
- [PATCH v3 6/9] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*, Bernhard Beschow, 2022/10/16
- [PATCH v3 8/9] hw/sd/sdhci: Implement Freescale eSDHC device model, Bernhard Beschow, 2022/10/16
- [PATCH v3 9/9] hw/ppc/e500: Add Freescale eSDHC to e500plat, Bernhard Beschow, 2022/10/16
- [PATCH v3 7/9] hw/ppc/e500: Implement pflash handling, Bernhard Beschow, 2022/10/16
- Re: [PATCH v3 7/9] hw/ppc/e500: Implement pflash handling, Peter Maydell, 2022/10/18