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[PATCH v2 20/43] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
From: |
Bernhard Beschow |
Subject: |
[PATCH v2 20/43] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS |
Date: |
Sat, 22 Oct 2022 17:04:45 +0200 |
PIIX_NUM_PIC_IRQS is assumed to be the same as ISA_NUM_IRQS, otherwise
inconsistencies can occur.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix3.c | 8 ++++----
include/hw/southbridge/piix.h | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index c6a8f1f27d..9de7287589 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -52,7 +52,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3,
int pirq, int level)
uint64_t mask;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -66,7 +66,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq,
int level)
int pic_irq;
pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ if (pic_irq >= ISA_NUM_IRQS) {
return;
}
@@ -98,7 +98,7 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque,
int pin)
int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
- if (irq < PIIX_NUM_PIC_IRQS) {
+ if (irq < ISA_NUM_IRQS) {
route.mode = PCI_INTX_ENABLED;
route.irq = irq;
} else {
@@ -130,7 +130,7 @@ static void piix3_write_config(PCIDevice *dev,
pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
piix3_set_irq_pic(piix3, pic_irq);
}
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index df3e0084c5..ae3b49fe93 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -32,7 +32,6 @@
*/
#define PIIX_RCR_IOPORT 0xcf9
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
struct PIIXState {
@@ -44,10 +43,10 @@ struct PIIXState {
* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
*
* PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
* pic_irq * PIIX_NUM_PIRQS + pirq
*/
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
#error "unable to encode pic state in 64bit in pic_levels."
#endif
uint64_t pic_levels;
--
2.38.1
- Re: [PATCH v2 14/43] hw/intc/i8259: Introduce i8259 proxy "isa-pic", (continued)
- [PATCH v2 15/43] hw/isa/piix3: Create ISA PIC in host device, Bernhard Beschow, 2022/10/22
- [PATCH v2 16/43] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2022/10/22
- [PATCH v2 17/43] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/10/22
- [PATCH v2 18/43] hw/isa/piix3: Remove unused include, Bernhard Beschow, 2022/10/22
- [PATCH v2 19/43] hw/isa/piix3: Allow board to provide PCI interrupt routes, Bernhard Beschow, 2022/10/22
- [PATCH v2 20/43] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS,
Bernhard Beschow <=
- [PATCH v2 21/43] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2022/10/22
- [PATCH v2 22/43] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4, Bernhard Beschow, 2022/10/22
- [PATCH v2 23/43] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_", Bernhard Beschow, 2022/10/22
- [PATCH v2 24/43] hw/isa/piix3: Rename typedef PIIX3State to PIIXState, Bernhard Beschow, 2022/10/22
- [PATCH v2 25/43] hw/mips/malta: Reuse dev variable, Bernhard Beschow, 2022/10/22