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[PATCH v2 40/43] hw/isa/piix: Consolidate IRQ triggering
From: |
Bernhard Beschow |
Subject: |
[PATCH v2 40/43] hw/isa/piix: Consolidate IRQ triggering |
Date: |
Sat, 22 Oct 2022 17:05:05 +0200 |
Speeds up PIIX4 which resolves an old TODO.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix.c | 26 +++-----------------------
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/hw/isa/piix.c b/hw/isa/piix.c
index 446105a7a1..4ced9995f9 100644
--- a/hw/isa/piix.c
+++ b/hw/isa/piix.c
@@ -84,27 +84,6 @@ static void piix_set_irq(void *opaque, int pirq, int level)
piix_set_irq_level(piix, pirq, level);
}
-static void piix4_set_irq(void *opaque, int irq_num, int level)
-{
- int i, pic_irq, pic_level;
- PIIXState *s = opaque;
- PCIBus *bus = pci_get_bus(&s->dev);
-
- /* now we change the pic irq level according to the piix irq mappings */
- /* XXX: optimize */
- pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
- if (pic_irq < ISA_NUM_IRQS) {
- /* The pic level is the logical OR of all the PCI irqs mapped to it. */
- pic_level = 0;
- for (i = 0; i < PIIX_NUM_PIRQS; i++) {
- if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
- pic_level |= pci_bus_get_irq_level(bus, i);
- }
- }
- qemu_set_irq(s->pic.in_irqs[pic_irq], pic_level);
- }
-}
-
/*
* Return the global irq number corresponding to a given device irq
* pin. We could also use the bus number to have a more precise mapping.
@@ -276,7 +255,7 @@ static int piix4_post_load(void *opaque, int version_id)
s->rcr = 0;
}
- return 0;
+ return piix3_post_load(opaque, version_id);
}
static int piix3_pre_save(void *opaque)
@@ -586,7 +565,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* RTC */
s->rtc.irq = qdev_get_gpio_in(DEVICE(&s->pic), s->rtc.isairq);
- pci_bus_irqs(pci_bus, piix4_set_irq, piix4_pci_slot_get_pirq, s,
+ pci_bus_irqs(pci_bus, piix_set_irq, piix4_pci_slot_get_pirq, s,
PIIX_NUM_PIRQS);
}
@@ -604,6 +583,7 @@ static void piix4_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ k->config_write = piix_write_config;
k->realize = piix4_realize;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
--
2.38.1
- [PATCH v2 32/43] hw/isa/piix4: Use ISA PIC device, (continued)
- [PATCH v2 32/43] hw/isa/piix4: Use ISA PIC device, Bernhard Beschow, 2022/10/22
- [PATCH v2 33/43] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Bernhard Beschow, 2022/10/22
- [PATCH v2 34/43] hw/isa/piix4: Rename reset control operations to match PIIX3, Bernhard Beschow, 2022/10/22
- [PATCH v2 35/43] hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_", Bernhard Beschow, 2022/10/22
- [PATCH v2 37/43] hw/isa/piix: Harmonize names of reset control memory regions, Bernhard Beschow, 2022/10/22
- [PATCH v2 36/43] hw/isa/piix3: Merge hw/isa/piix4.c, Bernhard Beschow, 2022/10/22
- [PATCH v2 38/43] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4, Bernhard Beschow, 2022/10/22
- [PATCH v2 39/43] hw/isa/piix: Rename functions to be shared for interrupt triggering, Bernhard Beschow, 2022/10/22
- [PATCH v2 40/43] hw/isa/piix: Consolidate IRQ triggering,
Bernhard Beschow <=
- [PATCH v2 41/43] hw/isa/piix: Share PIIX3 base class with PIIX4, Bernhard Beschow, 2022/10/22
- [PATCH v2 42/43] hw/isa/piix: Drop the "3" from the PIIX base class, Bernhard Beschow, 2022/10/22
- [PATCH v2 43/43] hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller, Bernhard Beschow, 2022/10/22