[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 09/32] hw/isa/piix3: Create USB controller in host device
From: |
Bernhard Beschow |
Subject: |
[PATCH 09/32] hw/isa/piix3: Create USB controller in host device |
Date: |
Sun, 4 Dec 2022 20:05:30 +0100 |
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221022150508.26830-13-shentey@gmail.com>
---
hw/i386/pc_piix.c | 7 ++-----
hw/isa/Kconfig | 1 +
hw/isa/piix3.c | 17 +++++++++++++++++
include/hw/southbridge/piix.h | 4 ++++
4 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index b97bff5674..22c1c5404c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -221,6 +220,8 @@ static void pc_init1(MachineState *machine,
pcms->bus = pci_bus;
pci_dev = pci_new_multifunction(-1, true, type);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -299,10 +300,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index af5ec9cd61..97b8ea7c06 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -36,6 +36,7 @@ config PIIX3
select I8257
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index c68e51ddad..af1c5b9859 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -299,6 +299,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
@@ -319,6 +320,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -352,6 +363,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -371,6 +387,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b1fa08dd2b..5367917182 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
RTCState rtc;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
--
2.38.1
- Re: [PATCH 01/32] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition, (continued)
- [PATCH 02/32] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader, Bernhard Beschow, 2022/12/04
- [PATCH 03/32] hw/isa/piix4: Correct IRQRC[A:D] reset values, Bernhard Beschow, 2022/12/04
- [PATCH 04/32] hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig, Bernhard Beschow, 2022/12/04
- [PATCH 05/32] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge, Bernhard Beschow, 2022/12/04
- [PATCH 06/32] hw/usb/hcd-uhci: Introduce TYPE_ defines for device models, Bernhard Beschow, 2022/12/04
- [PATCH 07/32] hw/i386/pc: Create RTC controllers in south bridges, Bernhard Beschow, 2022/12/04
- [PATCH 08/32] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2022/12/04
- [PATCH 09/32] hw/isa/piix3: Create USB controller in host device,
Bernhard Beschow <=
- [PATCH 10/32] hw/isa/piix3: Create power management controller in host device, Bernhard Beschow, 2022/12/04
- [PATCH 11/32] hw/core: Introduce proxy-pic, Bernhard Beschow, 2022/12/04
- [PATCH 13/32] hw/isa/piix3: Create IDE controller in host device, Bernhard Beschow, 2022/12/04
- [PATCH 14/32] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/12/04
- [PATCH 15/32] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Bernhard Beschow, 2022/12/04
- [PATCH 16/32] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4, Bernhard Beschow, 2022/12/04
- [PATCH 17/32] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4, Bernhard Beschow, 2022/12/04
- [PATCH 18/32] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_", Bernhard Beschow, 2022/12/04
- [PATCH 12/32] hw/isa/piix3: Create Proxy PIC in host device, Bernhard Beschow, 2022/12/04
- [PATCH 20/32] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional, Bernhard Beschow, 2022/12/04