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Re: [PATCH v5 00/31] Consolidate PIIX south bridges
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v5 00/31] Consolidate PIIX south bridges |
Date: |
Sun, 8 Jan 2023 19:28:28 +0100 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 |
On 8/1/23 16:12, Bernhard Beschow wrote:
Am 7. Januar 2023 23:57:32 UTC schrieb Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk>:
On 05/01/2023 14:31, Bernhard Beschow wrote:
Bernhard Beschow (28):
hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is
created
hw/i386/pc_piix: Allow for setting properties before realizing PIIX3
south bridge
hw/i386/pc: Create RTC controllers in south bridges
hw/i386/pc: No need for rtc_state to be an out-parameter
hw/isa/piix3: Create USB controller in host device
hw/isa/piix3: Create power management controller in host device
hw/intc/i8259: Make using the isa_pic singleton more type-safe
hw/intc/i8259: Introduce i8259 proxy "isa-pic"
hw/isa/piix3: Create ISA PIC in host device
hw/isa/piix3: Create IDE controller in host device
hw/isa/piix3: Wire up ACPI interrupt internally
hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS
hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4
hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4
hw/isa/piix3: Drop the "3" from PIIX base class
hw/isa/piix4: Make PIIX4's ACPI and USB functions optional
hw/isa/piix4: Remove unused inbound ISA interrupt lines
hw/isa/piix4: Use ISA PIC device
hw/isa/piix4: Reuse struct PIIXState from PIIX3
hw/isa/piix4: Rename reset control operations to match PIIX3
hw/isa/piix3: Merge hw/isa/piix4.c
hw/isa/piix: Harmonize names of reset control memory regions
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
hw/isa/piix: Rename functions to be shared for interrupt triggering
hw/isa/piix: Consolidate IRQ triggering
hw/isa/piix: Share PIIX3's base class with PIIX4
Phil - over to you!
Thanks for the review Mark!
Shall I respin? I could integrate my PCI series into this one in order to avoid
the outdated MIPS patches while still delivering a working series. Yes/No?
If you don't mind, that is certainly easier for me :)
- Re: [PATCH v5 24/31] hw/isa/piix4: Reuse struct PIIXState from PIIX3, (continued)
- [PATCH v5 27/31] hw/isa/piix: Harmonize names of reset control memory regions, Bernhard Beschow, 2023/01/05
- [PATCH v5 29/31] hw/isa/piix: Rename functions to be shared for interrupt triggering, Bernhard Beschow, 2023/01/05
- [PATCH v5 30/31] hw/isa/piix: Consolidate IRQ triggering, Bernhard Beschow, 2023/01/05
- [PATCH v5 31/31] hw/isa/piix: Share PIIX3's base class with PIIX4, Bernhard Beschow, 2023/01/05
- Re: [PATCH v5 00/31] Consolidate PIIX south bridges, Michael S. Tsirkin, 2023/01/05
- Re: [PATCH v5 00/31] Consolidate PIIX south bridges, Mark Cave-Ayland, 2023/01/07