[Qemu-commits] [qemu/qemu] d22d72: Fix operands of RECIP2.S and RECIP2.PS

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d22d7289877ecd3ef86570f6f6d0574da40711dc
      
https://github.com/qemu/qemu/commit/d22d7289877ecd3ef86570f6f6d0574da40711dc
  Author: Richard Sandiford <address@hidden>
  Date:   2012-08-27 (Mon, 27 Aug 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  Fix operands of RECIP2.S and RECIP2.PS

Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD.  RECIP2.D is already correct.

Signed-off-by: Richard Sandiford <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 13d24f49720a3e7b35a21222ef182c8513f139db
      
https://github.com/qemu/qemu/commit/13d24f49720a3e7b35a21222ef182c8513f139db
  Author: Richard Sandiford <address@hidden>
  Date:   2012-08-27 (Mon, 27 Aug 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  Fix order of CVT.PS.S operands

The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.

Signed-off-by: Richard Sandiford <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 05168674505153a641c7bfddb691d2eda11d13d1
      
https://github.com/qemu/qemu/commit/05168674505153a641c7bfddb691d2eda11d13d1
  Author: Richard Henderson <address@hidden>
  Date:   2012-08-27 (Mon, 27 Aug 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Streamline indexed cp1 memory addressing.

We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: b3167288367f79754b74ad933146e37938ebff13
      
https://github.com/qemu/qemu/commit/b3167288367f79754b74ad933146e37938ebff13
  Author: Richard Henderson <address@hidden>
  Date:   2012-08-27 (Mon, 27 Aug 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  mips-linux-user: Always support rdhwr.

The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <address@hidden>
Cc: Riku Voipio <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/d03c98d80ffb...b3167288367f