[Qemu-commits] [qemu/qemu] 044f4c: pseries: Fix incorrect initialization of interrupt...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 044f4c8b0ee90290b6cbbc616c4be3c8aeffcaab
      
https://github.com/qemu/qemu/commit/044f4c8b0ee90290b6cbbc616c4be3c8aeffcaab
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/xics.c

  Log Message:
  -----------
  pseries: Fix incorrect initialization of interrupt controller

Currently in the reset code for the XICS interrupt controller, we
initialize the pending_priority field to 0 (most favored, by XICS
convention).  This is incorrect, since there is no pending interrupt, it
should be set to least favored - 0xff.  At the moment our XICS
implementation doesn't get hurt by this edge case, but it does confuse the
upcoming kernel XICS implementation.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bf3bc4c4e992fb9914e2f1f7e8a569394d298b57
      
https://github.com/qemu/qemu/commit/bf3bc4c4e992fb9914e2f1f7e8a569394d298b57
  Author: Ben Herrenschmidt <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/spapr.c
    M hw/xics.c
    M hw/xics.h

  Log Message:
  -----------
  pseries: Use #define for XICS base irq number

Currently the lowest "real" irq number for the XICS irq controller (as
opposed to numbers reserved for IPIs and other special purposes) is
hard coded as 16 in two places - in xics_system_init() and in spapr.c.

As well as being generally bad practice, we're going to need to change this
number soon to fit in with the in-kernel XICS implementation.  This patch
adds a #define for this number to avoid future breakage.

Signed-off-by: Michael Ellerman <address@hidden>
Signed-off-by: Ben Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4aac82c34675fcbd3722dfc3a2d04c839215ec6b
      
https://github.com/qemu/qemu/commit/4aac82c34675fcbd3722dfc3a2d04c839215ec6b
  Author: Michael Ellerman <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/spapr.h
    M hw/spapr_rtas.c

  Log Message:
  -----------
  pseries: Return the token when we register an RTAS call

The kernel will soon be able to service some RTAS calls. However the
choice of tokens will still be up to userspace. To support this have
spapr_rtas_register() return the token that is allocated for an
RTAS call, that allows the calling code to tell the kernel what the
token value is.

Signed-off-by: Michael Ellerman <address@hidden>
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d36b66f7a420737dcc24de15b35a465ff6b1798d
      
https://github.com/qemu/qemu/commit/d36b66f7a420737dcc24de15b35a465ff6b1798d
  Author: Ben Herrenschmidt <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/spapr_rtas.c

  Log Message:
  -----------
  pseries: Allow RTAS tokens without a qemu handler

Kernel-based RTAS calls will not have a qemu handler, but will
still be registered in qemu in order to be assigned a token
number and appear in the device-tree.

Let's test for the name being NULL rather than the handler
when deciding to skip an entry while building the device-tree

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 500efa2319d1f1074b1d61e5ceb7a0fd61d0831d
      
https://github.com/qemu/qemu/commit/500efa2319d1f1074b1d61e5ceb7a0fd61d0831d
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/xics.c
    M trace-events

  Log Message:
  -----------
  pseries: Add tracepoints to the XICS interrupt controller

This patch adds tracing / debugging calls to the XICS interrupt controller
implementation used on the pseries machine.

Signed-off-by: Ben Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 22a2611c9cef4a8c8ad96fe17b3511a6cc5fb3a1
      
https://github.com/qemu/qemu/commit/22a2611c9cef4a8c8ad96fe17b3511a6cc5fb3a1
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/xics.c

  Log Message:
  -----------
  pseries: Split xics irq configuration from state information

Currently the XICS irq controller code has a per-irq state structure which
amongst other things includes whether the interrupt is level or message
triggered - this is configured by the platform code, and is not directly
visible to the guest.  This leads to a slightly awkward construct at reset
time where we need to reset everything in the state structure _except_ the
lsi/msi flag, which needs to retain the information given at platform init
time.

More importantly this flag will make matching the qemu state to the KVM
state for the upcoming in-kernel XICS implementation more awkward.  This
patch, therefore, removes this flag from the per-irq state structure,
instead adding a parallel array giving the lsi/msi configuration per irq.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 639e8102ae71ce2e46ebeffc6080767e573c0c56
      
https://github.com/qemu/qemu/commit/639e8102ae71ce2e46ebeffc6080767e573c0c56
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/Makefile.objs
    M hw/spapr.c
    M hw/spapr.h
    A hw/spapr_nvram.c
    M qemu-config.c

  Log Message:
  -----------
  pseries: Implement PAPR NVRAM

The PAPR specification requires a certain amount of NVRAM, accessed via
RTAS, which we don't currently implement in qemu.  This patch addresses
this deficiency, implementing the NVRAM as a VIO device, with some glue to
instantiate it automatically based on a machine option.

The machine option specifies a drive id, which is used to back the NVRAM,
making it persistent.  If nothing is specified, the driver instead simply
allocates space for the NVRAM, which will not be persistent

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4fd50339c0b55fa6387fa3c28f755c306997064c
      
https://github.com/qemu/qemu/commit/4fd50339c0b55fa6387fa3c28f755c306997064c
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF

  Log Message:
  -----------
  pseries: Update SLOF for NVRAM support

Now that we have implemented PAPR compatible NVRAM interfaces in qemu, this
updates the SLOF firmware to actually initialize and use the NVRAM as a
PAPR guest firmware is expected to do.

This SLOF update also includes an ugly but useful workaround for a bug in
the SLES11 installer which caused it to fail under KVM.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: dffb1dc29fb364aaafc41b34100a06517d7f065e
      
https://github.com/qemu/qemu/commit/dffb1dc29fb364aaafc41b34100a06517d7f065e
  Author: Bharat Bhushan <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  e500: Adding CCSR memory region

All devices are also placed under CCSR memory region.
The CCSR memory region is exported to pci device. The MSI interrupt
generation is the main reason to export the CCSR region to PCI device.
This put the requirement to move mpic under CCSR region, but logically
all devices should be under CCSR. So this patch places all emulated
devices under ccsr region.

Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3eddc1be1ccb26387f8f960f8a3d8c417064a91f
      
https://github.com/qemu/qemu/commit/3eddc1be1ccb26387f8f960f8a3d8c417064a91f
  Author: Bharat Bhushan <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    A hw/ppc/e500-ccsr.h
    M hw/ppc/e500.c
    M hw/ppce500_pci.c

  Log Message:
  -----------
  Adding BAR0 for e500 PCI controller

PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt generation 2) Allow CCSR registers access when configured
as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.

What I observed is that when guest read the size of BAR0 of host controller
configuration header (TYPE1 header) then it always reads it as 0. When
looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
device registering BAR0. I do not find any other controller also doing so
may they do not use BAR0.

There are two issues when BAR0 is not there (which I can think of):
1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
when reading the size of BAR0, it should give size as per real h/w.

2) Do we need this BAR0 inbound address translation?
  When BAR0 is of non-zero size then it will be configured for PCI
address space to local address(CCSR) space translation on inbound access.
The primary use case is for MSI interrupt generation. The device is
configured with an address offsets in PCI address space, which will be
translated to MSI interrupt generation MPIC registers. Currently I do
not understand the MSI interrupt generation mechanism in QEMU and also
IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
But this BAR0 will be used when using MSI on e500.

I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
but i do not see these being used for address translation.
So far that works because pci address space and local address space are 1:1
mapped. BAR0 inbound translation + ATMU translation will complete the address
translation of inbound traffic.

Signed-off-by: Bharat Bhushan <address@hidden>
[agraf: fix double variable assignment w/o read]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8b1853e7d8c2bf8c6a9f023ab98ba0e8a38bd086
      
https://github.com/qemu/qemu/commit/8b1853e7d8c2bf8c6a9f023ab98ba0e8a38bd086
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/spapr_iommu.c

  Log Message:
  -----------
  pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs

The PAPR specification requires that every bus or device mediated by the
IOMMU have a unique Logical IO Bus Number (LIOBN).  This patch adds a check
to enforce this, which will help catch errors in configuration earlier.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 38898d7ed803cee5105246150725487add78cbd7
      
https://github.com/qemu/qemu/commit/38898d7ed803cee5105246150725487add78cbd7
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: Remove unused code

The openpic code had a few WIP bits left that nobody reanimated within
the last few years. Remove that code.

Signed-off-by: Alexander Graf <address@hidden>
Acked-by: Hervé Poussineau <address@hidden>


  Commit: cdbb912a6f8b5f325df3a6fd42cb2843032050c9
      
https://github.com/qemu/qemu/commit/cdbb912a6f8b5f325df3a6fd42cb2843032050c9
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c
    M hw/ppc/e500.c

  Log Message:
  -----------
  mpic: Unify numbering scheme

MPIC interrupt numbers in Linux (device tree) and in QEMU are different,
because QEMU takes the sparseness of the IRQ number space into account.

Remove that cleverness and instead assume a flat number space. This makes
the code easier to understand, because we are actually aligned with Linux
on the view of our worlds.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: b9b2aaa3c6926cf8af21fe75457ca6c6e0dc1f5d
      
https://github.com/qemu/qemu/commit/b9b2aaa3c6926cf8af21fe75457ca6c6e0dc1f5d
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: update to proper memory api

The openpic code was still using the old mmio memory api. Convert it to
be a generic memory api user and clean up some code that becomes redundant
that way.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: a285f1ca703a434fa8edf584f94a1dc29067ab29
      
https://github.com/qemu/qemu/commit/a285f1ca703a434fa8edf584f94a1dc29067ab29
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: combine mpic and openpic src handlers

The MPIC source irq handler suddenly became identical to the standard
OpenPIC source irq handler. Combine them into the same function.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 780d16b77f992db81e90b7dd7474a9397ce393b9
      
https://github.com/qemu/qemu/commit/780d16b77f992db81e90b7dd7474a9397ce393b9
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: Convert subregions to memory api

The "openpic" controller is currently using one big region and does
subregion dispatching manually. Move this to the memory api.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5861a33898bbddfd1a80c2e202cb9352e3b1ba62
      
https://github.com/qemu/qemu/commit/5861a33898bbddfd1a80c2e202cb9352e3b1ba62
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c
    M hw/openpic.h

  Log Message:
  -----------
  openpic: combine mpic and openpic irq raise functions

The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical,
just that the MPIC one can also raise critical interrupts.

Combine those two and check for critical raise capability during runtime.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: c38c0b8ad0551e470984f2ae7e8e54aae304ed4b
      
https://github.com/qemu/qemu/commit/c38c0b8ad0551e470984f2ae7e8e54aae304ed4b
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: merge mpic and openpic timer handling

The openpic and mpic timer handling code is basically the same.
Merge them.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 825463b38414c9afb657caee1ce20eff2d521317
      
https://github.com/qemu/qemu/commit/825463b38414c9afb657caee1ce20eff2d521317
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: combine openpic and mpic reset functions

The openpic and mpic reset handlers are almost identical. Combine
them and extract the differences into state variables.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 35732cb41e8f8608bb0fd6ae023daee56d439bf1
      
https://github.com/qemu/qemu/commit/35732cb41e8f8608bb0fd6ae023daee56d439bf1
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: unify memory api subregions

The only difference between the "openpic" and "mpic" memory api subregion
descriptors is the endianness. Unify them as openpic accessors with explicit
endianness markers in their names.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: e1d10851522d7262a266f95d54c48eb2b1d8eb9b
      
https://github.com/qemu/qemu/commit/e1d10851522d7262a266f95d54c48eb2b1d8eb9b
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: remove unused type variable

The openpic source irqs are carrying around a type indicator that
is never accessed by anything. Remove it.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1945dbc15f0f1ffdc9a10526448e9eba7c599d98
      
https://github.com/qemu/qemu/commit/1945dbc15f0f1ffdc9a10526448e9eba7c599d98
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: convert simple reg operations to builtin bitops

The openpic code has its own bitmap code to access bits inside of a
bitmap. However, that is overkill when we simply want to check for a
bit inside of a uint32_t.

So instead, let's use normal bit masks and C builtin shifts and ands.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6d544ee8ac2097c87fc97b53d6a1310d9daa0562
      
https://github.com/qemu/qemu/commit/6d544ee8ac2097c87fc97b53d6a1310d9daa0562
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: rename openpic_t to OpenPICState

Rename the openpic_t struct to OpenPICState, so it adheres better to
the current coding style rules.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5bac0701113f4de4fee053a3939b0f569a04b88c
      
https://github.com/qemu/qemu/commit/5bac0701113f4de4fee053a3939b0f569a04b88c
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c
    M hw/openpic.h
    M hw/ppc/e500.c
    M hw/ppc_newworld.c

  Log Message:
  -----------
  openpic: remove irq_out

The current openpic emulation contains half-ready code for bypass mode.
Remove it, so that when someone wants to finish it they can start from a
clean state.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: d0b7263134dfd4d487698b639f2069951f3fdb26
      
https://github.com/qemu/qemu/commit/d0b7263134dfd4d487698b639f2069951f3fdb26
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c
    M hw/openpic.h
    M hw/ppc/e500.c
    M hw/ppc_newworld.c

  Log Message:
  -----------
  openpic: convert to qdev

This patch converts the OpenPIC device to qdev. Along the way it
renames the "openpic" target to "raven" and the "mpic" target to
"fsl_mpic_20", to better reflect the actual models they implement.

This way we have a generic OpenPIC device now that can handle
different flavors of the OpenPIC specification.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: dbbbfd6058dda61f57d1f72133aa54eb27330411
      
https://github.com/qemu/qemu/commit/dbbbfd6058dda61f57d1f72133aa54eb27330411
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: make brr1 model specific

Now that we can properly distinguish between openpic model differences,
let's move brr1 out of the raven code path.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 732aa6ec2639ace8bcb0b27b9c0d71103bd1d153
      
https://github.com/qemu/qemu/commit/732aa6ec2639ace8bcb0b27b9c0d71103bd1d153
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: add Shared MSI support

The OpenPIC allows MSI access through shared MSI registers. Implement
them for the MPC8544 MPIC, so we can support MSIs.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: a911b7a92064d17b862ae85fe8e5ec91b7ba1aa9
      
https://github.com/qemu/qemu/commit/a911b7a92064d17b862ae85fe8e5ec91b7ba1aa9
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  PPC: e500: Add MSI support

Now that our interrupt controller supports MSIs, let's expose that feature
to the guest through the device tree!

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 997505065dc92e533debf5cb23012ba4e673d387
      
https://github.com/qemu/qemu/commit/997505065dc92e533debf5cb23012ba4e673d387
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppce500_pci.c

  Log Message:
  -----------
  PPC: e500: Declare pci bridge as bridge

The new PCI host bridge device needs to identify itself as PCI host bridge.
Declare it as such.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 68d1e1f52d73ddcec4b0358f269d9a8c2ea216d9
      
https://github.com/qemu/qemu/commit/68d1e1f52d73ddcec4b0358f269d9a8c2ea216d9
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/msix.c

  Log Message:
  -----------
  MSI-X: Fix endianness

The MSI-X vector tables are usually stored in little endian in memory,
so let's mark the accessors as such.

This fixes MSI-X on e500 for me.

Signed-off-by: Alexander Graf <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>


  Commit: dbe30e13e87a71e85e88ae3ffd3460173cbc8193
      
https://github.com/qemu/qemu/commit/dbe30e13e87a71e85e88ae3ffd3460173cbc8193
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: fix minor coding style issues

This patch removes all remaining occurences of spaces before function
parameter indicating parenthesis.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 76aec1f8b6549d14576a3eb739c731df8f678ffb
      
https://github.com/qemu/qemu/commit/76aec1f8b6549d14576a3eb739c731df8f678ffb
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/openpic.c

  Log Message:
  -----------
  openpic: Accelerate pending irq search

When we're done with one interrupt, we need to search for the next pending
interrupt in the queue. This search has grown quite big now that we have
more than 256 possible irq lines.

So let's memorize how many interrupts we have pending in our bitmaps, so
that we can always bail out in the usual case - the one where we're all done.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: eafb325fb11af21ed9df3f5a310fd26e70954318
      
https://github.com/qemu/qemu/commit/eafb325fb11af21ed9df3f5a310fd26e70954318
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppce500_pci.c

  Log Message:
  -----------
  PPC: E500: PCI: Make first slot qdev settable

Today the first slot id in our e500 pci implementation is hardcoded to
0x11. Keep it there as default, but allow users to change the default to
a different id.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 05f57d9de8e99bf5f7ca762c6dc2f1e054c2074c
      
https://github.com/qemu/qemu/commit/05f57d9de8e99bf5f7ca762c6dc2f1e054c2074c
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppce500_pci.c

  Log Message:
  -----------
  PPC: E500: PCI: Make IRQ calculation more generic

The IRQ line calculation is more or less hardcoded today. Instead, let's
write it as an algorithmic function that theoretically allows an arbitrary
number of PCI slots.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 347dd79dccf41a679115213da673dfd06c4c8cc8
      
https://github.com/qemu/qemu/commit/347dd79dccf41a679115213da673dfd06c4c8cc8
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  PPC: E500: Generate dt pci irq map dynamically

Today we're hardcoding the PCI interrupt map in the e500 machine file.
Instead, let's write it dynamically so that different machine types
can have different slot properties.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 492ec48dc2d99ca13b24d554e1970af7e2581e23
      
https://github.com/qemu/qemu/commit/492ec48dc2d99ca13b24d554e1970af7e2581e23
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/e500plat.c
    M hw/ppc/mpc8544ds.c

  Log Message:
  -----------
  PPC: E500: Move PCI slot information into params

We have a params struct that allows us to expose differences between
e500 machine models. Include PCI slot information there, so we can have
different machines with different PCI slot topology.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3bb7e02a9725a24e5bf915b35f914f82f5b07a1f
      
https://github.com/qemu/qemu/commit/3bb7e02a9725a24e5bf915b35f914f82f5b07a1f
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500plat.c

  Log Message:
  -----------
  PPC: E500plat: Make a lot of PCI slots available

The ppce500 machine doesn't have to stick to hardware limitations,
as it's defined as being fully device tree based.

Thus we can change the initial PCI slot ID to 0x1 which gives us a
whopping 31 PCI devices we can support with this machine now!

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9e2c12988bebca7b99c0cd064b23fb7ea6643c86
      
https://github.com/qemu/qemu/commit/9e2c12988bebca7b99c0cd064b23fb7ea6643c86
  Author: Alexander Graf <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppce500_pci.c
    A hw/ppce500_pci.h

  Log Message:
  -----------
  PPC: e500: pci: Export slot2irq calculation

We need the calculation method to get from a PCI slot ID to its respective
interrupt line twice. Once in the internal map function and once when
assembling the device tree.

So let's extract the calculation to a separate function that can be called
by both users.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: b162d02e9450201c656edce290f33994a6d2ad33
      
https://github.com/qemu/qemu/commit/b162d02e9450201c656edce290f33994a6d2ad33
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  target-ppc: Don't use hwaddr to represent hardware state

The hwaddr type is somewhat vaguely defined as being able to contain bus
addresses on the widest possible bus in the system.  For that reason it's
discouraged for representing specific pieces of persistent hardware state,
which should instead use an explicit width type that matches the bits
available in real hardware.  In particular, because of the possibility that
the size of hwaddr might change if different buses are added to the target
in future, it's not suitable for use in vm state descriptions for savevm
and migration.

This patch purges such unwise uses of hwaddr from the ppc target code,
which turns out to be just one.  The ppcemb_tlb_t struct, used on a number
of embedded ppc models to represent a TLB entry contains a hwaddr for the
real address field.  This patch changes it to be a fixed uint64_t which is
suitable enough for all machine types which use this structure.

Other uses of hwaddr in CPUPPCState turn out not to be problematic:
htab_base and htab_mask are just used for the convenience of the TCG code;
the underlying machine state is the SDR1 register, which is stored with
a suitable type already.  Likewise the mpic_cpu_base field is only used
internally and does not represent fundamental hardware state which needs to
be saved.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a64ae610b978dfd8ccfb7f6c5d4cfe62d7542fbd
      
https://github.com/qemu/qemu/commit/a64ae610b978dfd8ccfb7f6c5d4cfe62d7542fbd
  Author: David Gibson <address@hidden>
  Date:   2012-12-14 (Fri, 14 Dec 2012)

  Changed paths:
    M hw/spapr_nvram.c

  Log Message:
  -----------
  pseries: Increase default NVRAM size

If no image file for NVRAM is specified, the pseries machine currently
creates a 16K non-persistent NVRAM by default.  This basically works, but
is not large enough for current firmware and guest kernels to create all
the NVRAM partitions they would like to.  Increasing the default size to
64K addresses this and stops the guest generating error messages.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6d4e18925a65306afabaad7b63a4588c18919e99
      
https://github.com/qemu/qemu/commit/6d4e18925a65306afabaad7b63a4588c18919e99
  Author: Blue Swirl <address@hidden>
  Date:   2012-12-15 (Sat, 15 Dec 2012)

  Changed paths:
    M hw/msix.c
    M hw/openpic.c
    M hw/openpic.h
    M hw/ppc/Makefile.objs
    A hw/ppc/e500-ccsr.h
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/e500plat.c
    M hw/ppc/mpc8544ds.c
    M hw/ppc_newworld.c
    M hw/ppce500_pci.c
    A hw/ppce500_pci.h
    M hw/spapr.c
    M hw/spapr.h
    M hw/spapr_iommu.c
    A hw/spapr_nvram.c
    M hw/spapr_rtas.c
    M hw/xics.c
    M hw/xics.h
    M pc-bios/README
    M pc-bios/slof.bin
    M qemu-config.c
    M roms/SLOF
    M target-ppc/cpu.h
    M trace-events

  Log Message:
  -----------
  Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf

* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (40 commits)
  pseries: Increase default NVRAM size
  target-ppc: Don't use hwaddr to represent hardware state
  PPC: e500: pci: Export slot2irq calculation
  PPC: E500plat: Make a lot of PCI slots available
  PPC: E500: Move PCI slot information into params
  PPC: E500: Generate dt pci irq map dynamically
  PPC: E500: PCI: Make IRQ calculation more generic
  PPC: E500: PCI: Make first slot qdev settable
  openpic: Accelerate pending irq search
  openpic: fix minor coding style issues
  MSI-X: Fix endianness
  PPC: e500: Declare pci bridge as bridge
  PPC: e500: Add MSI support
  openpic: add Shared MSI support
  openpic: make brr1 model specific
  openpic: convert to qdev
  openpic: remove irq_out
  openpic: rename openpic_t to OpenPICState
  openpic: convert simple reg operations to builtin bitops
  openpic: remove unused type variable
  ...


Compare: https://github.com/qemu/qemu/compare/659f807c0a70...6d4e18925a65