[Qemu-commits] [qemu/qemu] 229a13: target-arm: Fix return address for A64 BRK instruc...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 229a138d740142885dd4e7063e25147d7f71fdef
      
https://github.com/qemu/qemu/commit/229a138d740142885dd4e7063e25147d7f71fdef
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Fix return address for A64 BRK instructions

When we take an exception resulting from a BRK instruction,
the architecture requires that the "preferred return address"
reported to the exception handler is the address of the BRK
itself, not the following instruction (like undefined
insns, and in contrast with SVC, HVC and SMC). Follow this,
rather than incorrectly reporting the address of the following
insn.

(We do get this correct for the A32/T32 BKPT insns.)

Signed-off-by: Peter Maydell <address@hidden>
Cc: address@hidden


  Commit: 503006983a19be0b481946afac2cab0bdd21f124
      
https://github.com/qemu/qemu/commit/503006983a19be0b481946afac2cab0bdd21f124
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Collect up the debug cp register definitions

At the moment we have a mixed set of mostly dummy register
definitions for various debug related registers which have
been added piecemeal in order to get Linux kernels to boot.
In preparation for actually implementing debug support,
bring them all together into one place.

This commit doesn't change behaviour: we still expose
exactly the same registers and behaviour to the guest
in all configurations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 58a1d8ceabbbf0ddaa8d6d81faa2f77816d35e18
      
https://github.com/qemu/qemu/commit/58a1d8ceabbbf0ddaa8d6d81faa2f77816d35e18
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14

Currently the STATE_BOTH shorthand for allowing a single reginfo struct
to define handling for both AArch32 and AArch64 views of a register
only permits this where the AArch32 view is in cp15. It turns out that
the debug registers in cp14 also have neatly lined up encodings;
allow these also to share reginfo structs by permitting a STATE_BOTH
reginfo to specify the .cp field (and continue to default to 15 if
it is not specified).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 10aae1049fe90b84798af2751051ea896437a831
      
https://github.com/qemu/qemu/commit/10aae1049fe90b84798af2751051ea896437a831
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Provide both 32 and 64 bit versions of debug registers

Bring the 32 bit and 64 bit views of the debug registers into
line by providing the same set of registers in both cases.
(This still isn't a complete set, but it is consistent.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 48eb3ae64b3e17151cf8f42af185e6f43baf707b
      
https://github.com/qemu/qemu/commit/48eb3ae64b3e17151cf8f42af185e6f43baf707b
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Adjust debug ID registers per-CPU

Allow each CPU type to specify the value for the debug ID
registers, by putting them in the ARMCPU struct, and use
the resulting information to only expose the correct number
of watchpoint and breakpoint registers for the CPU.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 4051e12c5df1c46b542b28ed43f1614a42245ecf
      
https://github.com/qemu/qemu/commit/4051e12c5df1c46b542b28ed43f1614a42245ecf
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/op_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Don't allow AArch32 to access RES0 CPSR bits

The CPSR has a new-in-v8 execution state bit (IL), and
also some state which has effects in AArch32 but appears
only in the SPSR format (SS) but is RES0 in the CPSR.

Add the IL bit to CPSR_EXEC, and enforce that guest direct
reads and writes to CPSR can't read or write the RES0
bits, so the guest can't get at the SS bit which we store
in uncached_cpsr. This includes not permitting exception
returns to copy reserved bits from an SPSR into CPSR.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 662cefb7753c1f04d960b443c60e7622c83144d3
      
https://github.com/qemu/qemu/commit/662cefb7753c1f04d960b443c60e7622c83144d3
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correctly handle PSTATE.SS when taking exception to AArch32

When an exception is taken to AArch32, we must clear the PSTATE.SS
bit for the exception handler, and must also ensure that the SS bit
is not set in the value saved to SPSR_<mode>. Achieve both of these
aims by clearing the bit in uncached_cpsr before saving it to the SPSR.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 3a2982038afa0f04fc99b259e8ad8c18be0b04cb
      
https://github.com/qemu/qemu/commit/3a2982038afa0f04fc99b259e8ad8c18be0b04cb
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Set PSTATE.SS correctly on exception return from AArch64

Set the PSTATE.SS bit correctly on exception returns from AArch64,
as required by the debug single-step functionality.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: cc9c1ed14e876d724107fe72f74dcac71a003fbc
      
https://github.com/qemu/qemu/commit/cc9c1ed14e876d724107fe72f74dcac71a003fbc
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb

If gen_goto_tb() decides not to link the two TBs, then the
fallback path generates unnecessary code:
 * if singlestep is enabled then we generate unreachable code
   after the gen_exception_internal(EXCP_DEBUG)
 * if singlestep is disabled then we will generate exit_tb(0)
   twice, once in gen_goto_tb() and once coming out of the
   main loop with is_jmp set to DISAS_JUMP

Correct these deficiencies by only emitting exit_tb() in the
non-singlestep case, in which case we can use DISAS_TB_JUMP
to suppress the main-loop exit_tb().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 7ea47fe7be86faed4f38f0093ca1226b9b6043eb
      
https://github.com/qemu/qemu/commit/7ea47fe7be86faed4f38f0093ca1226b9b6043eb
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.h
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Implement ARMv8 single-step handling for A64 code

Implement ARMv8 software single-step handling for A64 code:
correctly update the single-step state machine and generate
debug exceptions when stepping A64 code.

This patch has no behavioural change since MDSCR_EL1.SS can't
be set by the guest yet.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 50225ad0c185a16c472b3dce984c312e4399a3ef
      
https://github.com/qemu/qemu/commit/50225ad0c185a16c472b3dce984c312e4399a3ef
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Implement ARMv8 single-stepping for AArch32 code

ARMv8 single-stepping requires the exception level that controls
the single-stepping to be in AArch64 execution state, but the
code being stepped may be in AArch64 or AArch32. Implement the
necessary support code for single-stepping AArch32 code.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 0e5e8935bb93e80bb95dc79f51f5bf874ba2ab99
      
https://github.com/qemu/qemu/commit/0e5e8935bb93e80bb95dc79f51f5bf874ba2ab99
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement MDSCR_EL1 as having state

Now that all the new code to support single-stepping is in
place, wire up the guest-visible MDSCR_EL1, so the guest
can enable single-stepping.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: a65c9c17cef16bcb98ec6cf4feb8676c1a2d1168
      
https://github.com/qemu/qemu/commit/a65c9c17cef16bcb98ec6cf4feb8676c1a2d1168
  Author: Christoffer Dall <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/arm/virt.c
    M target-arm/kvm-consts.h

  Log Message:
  -----------
  target-arm: Rename QEMU PSCI v0.1 definitions

The function IDs for PSCI v0.1 are exported by KVM and defined as
KVM_PSCI_FN_<something>.  To build using these defines in non-KVM code,
QEMU defines these IDs locally and check their correctness against the
KVM headers when those are available.

However, the naming scheme used for QEMU (almost) clashes with the PSCI
v0.2 definitions from Linux so to avoid unfortunate naming when we
introduce local PSCI v0.2 defines, rename the current local defines with
QEMU_ prependend and clearly identify the PSCI version as v0.1 in the
defines.

Cc: address@hidden
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 863714ba6cdc09d1a84069815dc67c8da66b0a29
      
https://github.com/qemu/qemu/commit/863714ba6cdc09d1a84069815dc67c8da66b0a29
  Author: Christoffer Dall <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/arm/virt.c
    M target-arm/kvm-consts.h

  Log Message:
  -----------
  arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2

The current code supplies the PSCI v0.1 function IDs in the DT even when
KVM uses PSCI v0.2.

This will break guest kernels that only support PSCI v0.1 as they will
use the IDs provided in the DT.  Guest kernels with PSCI v0.2 support
are not affected by this patch, because they ignore the function IDs in
the device tree and rely on the architecture definition.

Define QEMU versions of the constants and check that they correspond to
the Linux defines on Linux build hosts.  After this patch, both guest
kernels with PSCI v0.1 support and guest kernels with PSCI v0.2 should
work.

Tested on TC2 for 32-bit and APM Mustang for 64-bit (aarch64 guest
only).  Both cases tested with 3.14 and linus/master and verified I
could bring up 2 cpus with both guest kernels.  Also tested 32-bit with
a 3.14 host kernel with only PSCI v0.1 and both guests booted here as
well.

Cc: address@hidden
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0
      
https://github.com/qemu/qemu/commit/f7838b5290de03f7cb2dbee5bd1ceae67b4a5ef0
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  arm: cortex-a9: Fix cache-line size and associativity

For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.

QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 235e74afcb85285a8e35e75f0cb6e6811267bb75
      
https://github.com/qemu/qemu/commit/235e74afcb85285a8e35e75f0cb6e6811267bb75
  Author: Richard W.M. Jones <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/core/loader.c
    M include/hw/loader.h

  Log Message:
  -----------
  loader: Add load_image_gzipped function.

As the name suggests this lets you load a ROM/disk image that is
gzipped.  It is uncompressed before storing it in guest memory.

Signed-off-by: Richard W.M. Jones <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: removed stray space before ')']
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6f5d3cbe8892367026526a7deed0ceecc700a7ad
      
https://github.com/qemu/qemu/commit/6f5d3cbe8892367026526a7deed0ceecc700a7ad
  Author: Richard W.M. Jones <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  aarch64: Allow -kernel option to take a gzip-compressed kernel.

On aarch64 it is the bootloader's job to uncompress the kernel.  UEFI
and u-boot bootloaders do this automatically when the kernel is
gzip-compressed.

However the qemu -kernel option does not do this.  The following
command does not work:

  qemu-system-aarch64 [...] -kernel /boot/vmlinuz

because it tries to execute the gzip-compressed data.

This commit lets gzip-compressed kernels be uncompressed
transparently.

Currently this is only done when emulating aarch64.

Signed-off-by: Richard W.M. Jones <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e9322dea3f72019f8c41139ff2d5a159db87a3f
      
https://github.com/qemu/qemu/commit/6e9322dea3f72019f8c41139ff2d5a159db87a3f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/arm.h

  Log Message:
  -----------
  arm: armv7m: Rename address_space_mem -> system_memory

This argument is a MemoryRegion and not an AddressSpace.

"Address space" means something quite different to "memory region"
in QEMU parlance so rename the variable to reduce confusion.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14a906f755f77b325666d67e071c572478d06067
      
https://github.com/qemu/qemu/commit/14a906f755f77b325666d67e071c572478d06067
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-08-19 (Tue, 19 Aug 2014)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  arm: stellaris: Remove misleading address_space_mem var

It's a MemoryRegion and not an AddressSpace. But since it's single use,
just inline the get_system_memory() call to the only usage to remove it.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2656eb7c599e306b95bad82b1372fc49ba3088f6
      
https://github.com/qemu/qemu/commit/2656eb7c599e306b95bad82b1372fc49ba3088f6
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-20 (Wed, 20 Aug 2014)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/arm/boot.c
    M hw/arm/stellaris.c
    M hw/arm/virt.c
    M hw/core/loader.c
    M include/hw/arm/arm.h
    M include/hw/loader.h
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/internals.h
    M target-arm/kvm-consts.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140819' 
into staging

target-arm:
 * fix preferred return address for A64 BRK insn
 * implement AArch64 single-stepping
 * support loading gzip compressed AArch64 kernels
 * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2
 * minor cleanups

# gpg: Signature made Tue 19 Aug 2014 19:04:09 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140819:
  arm: stellaris: Remove misleading address_space_mem var
  arm: armv7m: Rename address_space_mem -> system_memory
  aarch64: Allow -kernel option to take a gzip-compressed kernel.
  loader: Add load_image_gzipped function.
  arm: cortex-a9: Fix cache-line size and associativity
  arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2
  target-arm: Rename QEMU PSCI v0.1 definitions
  target-arm: Implement MDSCR_EL1 as having state
  target-arm: Implement ARMv8 single-stepping for AArch32 code
  target-arm: Implement ARMv8 single-step handling for A64 code
  target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb
  target-arm: Set PSTATE.SS correctly on exception return from AArch64
  target-arm: Correctly handle PSTATE.SS when taking exception to AArch32
  target-arm: Don't allow AArch32 to access RES0 CPSR bits
  target-arm: Adjust debug ID registers per-CPU
  target-arm: Provide both 32 and 64 bit versions of debug registers
  target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14
  target-arm: Collect up the debug cp register definitions
  target-arm: Fix return address for A64 BRK instructions

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/302fa283789a...2656eb7c599e