[Qemu-commits] [qemu/qemu] fa0d2f: target-mips: define ISA

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[Qemu-commits] [qemu/qemu] fa0d2f: target-mips: define ISA_MIPS64R6

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] fa0d2f: target-mips: define ISA_MIPS64R6
Date:	Wed, 22 Oct 2014 05:30:07 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fa0d2f69e716cdc67012109f1f991c32ab961082
      
https://github.com/qemu/qemu/commit/fa0d2f69e716cdc67012109f1f991c32ab961082
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/mips-defs.h

  Log Message:
  -----------
  target-mips: define ISA_MIPS64R6

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: fecd2646957bf7c2e0612c6b218903d982560014
      
https://github.com/qemu/qemu/commit/fecd2646957bf7c2e0612c6b218903d982560014
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: signal RI Exception on instructions removed in R6

Signal Reserved Instruction Exception on instructions that do not exist in R6.
In this commit the following groups of preR6 instructions are marked as deleted:
- Floating Point Paired Single
- Floating Point Compare
- conditional moves / branches on FPU conditions
- branch likelies
- unaligned loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: b691d9d2a0c13ad27df44964f6fdd34d5f259607
      
https://github.com/qemu/qemu/commit/b691d9d2a0c13ad27df44964f6fdd34d5f259607
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add SELEQZ and SELNEZ instructions

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: James Hogan <address@hidden>


  Commit: 4368b29a26ebd13db95325b3511c0157ea9826f0
      
https://github.com/qemu/qemu/commit/4368b29a26ebd13db95325b3511c0157ea9826f0
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: move LL and SC instructions

The encoding of LL and SC instruction has changed in MIPS32 Release 6.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: James Hogan <address@hidden>


  Commit: 099e5b4d9fe99860b5533d09fac7ac8b64c12b53
      
https://github.com/qemu/qemu/commit/099e5b4d9fe99860b5533d09fac7ac8b64c12b53
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: extract decode_opc_special* from decode_opc

Creating separate decode functions for special, special2 and special3
instructions to ease adding new R6 instructions and removing legacy
instructions.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 10dc65dbb83829590e79216a86c2ee168be3bf0b
      
https://github.com/qemu/qemu/commit/10dc65dbb83829590e79216a86c2ee168be3bf0b
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: split decode_opc_special* into *_r6 and *_legacy

For better code readability and to avoid 'if' statements for all R6 and preR6
instructions whose opcodes are the same - decode_opc_special* functions are
split into functions with _r6 and _legacy suffixes.

*_r6 functions will contain instructions which were introduced in R6.
*_legacy functions will contain instructions which were removed in R6.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: fac5a0733013f4e148b406056526f2208464d799
      
https://github.com/qemu/qemu/commit/fac5a0733013f4e148b406056526f2208464d799
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: signal RI Exception on DSP and Loongson instructions

Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: bf7910c6b1bc47517a9d7a6049d97d056e014eb0
      
https://github.com/qemu/qemu/commit/bf7910c6b1bc47517a9d7a6049d97d056e014eb0
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: move PREF, CACHE, LLD and SCD instructions

The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: b42ee5e1d97c035b832f9b5c8e0decd286ec091c
      
https://github.com/qemu/qemu/commit/b42ee5e1d97c035b832f9b5c8e0decd286ec091c
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: redefine Integer Multiply and Divide instructions

Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 4267d3e6e0d7be184ef343919640e7be6ae34e71
      
https://github.com/qemu/qemu/commit/4267d3e6e0d7be184ef343919640e7be6ae34e71
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6

Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping
with MIPS32R6 SDBBP.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 01f72885794124f94b24d97daf3c8630424cfd79
      
https://github.com/qemu/qemu/commit/01f72885794124f94b24d97daf3c8630424cfd79
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Status.UX/SX/KX enable 32-bit address wrapping

In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 15eacb9b525ad7f6b9326eeb8eeb151721d66570
      
https://github.com/qemu/qemu/commit/15eacb9b525ad7f6b9326eeb8eeb151721d66570
  Author: Yongbok Kim <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 31837be3eefed955504a3396d9baef8bcdec672e
      
https://github.com/qemu/qemu/commit/31837be3eefed955504a3396d9baef8bcdec672e
  Author: Yongbok Kim <address@hidden>
  Date:   2014-10-13 (Mon, 13 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add compact and CP1 branches

Introduce MIPS32R6 Compact Branch instructions which do not have delay slot -
they have forbidden slot instead. However, current implementation does not
support forbidden slot yet.

Add also BC1EQZ and BC1NEZ instructions.

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d4ea6acdf60db1d8373543e1557ba908f5d5479b
      
https://github.com/qemu/qemu/commit/d4ea6acdf60db1d8373543e1557ba908f5d5479b
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add AUI, LSA and PCREL instruction families

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 2d31e0607d0038b0c3450bb9624b0639e1181b1a
      
https://github.com/qemu/qemu/commit/2d31e0607d0038b0c3450bb9624b0639e1181b1a
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: add functions corresponding to IEEE-2008 min/maxNumMag

Add abs argument to the existing softfloat minmax() function and define
new float{32,64}_{min,max}nummag functions.

minnummag(x,y) returns x if |x| < |y|,
         returns y if |y| < |x|,
         otherwise minnum(x,y)

maxnummag(x,y) returns x if |x| > |y|,
         returns y if |y| > |x|,
         otherwise maxnum(x,y)

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: e7f16abbc5b4058180e14c5912ef319f222b39fc
      
https://github.com/qemu/qemu/commit/e7f16abbc5b4058180e14c5912ef319f222b39fc
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add new Floating Point instructions

In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced
MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions.

In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant
i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been
updated yet.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 3f4938833c21a394bf4630c163467b401d1b3ff6
      
https://github.com/qemu/qemu/commit/3f4938833c21a394bf4630c163467b401d1b3ff6
  Author: Yongbok Kim <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add new Floating Point Comparison instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: ddc584bdb5375f260e7dcec3831d1bb32f665d25
      
https://github.com/qemu/qemu/commit/ddc584bdb5375f260e7dcec3831d1bb32f665d25
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: do not allow Status.FR=0 mode in 64-bit FPU

Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 0aefa33318be6a9a6438c31921d426a755f1a2e9
      
https://github.com/qemu/qemu/commit/0aefa33318be6a9a6438c31921d426a755f1a2e9
  Author: Yongbok Kim <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: 9fba15004233950365c0273d21b3d91e8a18f97f
      
https://github.com/qemu/qemu/commit/9fba15004233950365c0273d21b3d91e8a18f97f
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  mips_malta: update malta's pseudo-bootloader - replace JR with JALR

JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>


  Commit: a773cc7970432d1bad3835f3112512cabad3f367
      
https://github.com/qemu/qemu/commit/a773cc7970432d1bad3835f3112512cabad3f367
  Author: Leon Alrae <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: a83bddd60de0dfdbc04c6683c2701682073af5cf
      
https://github.com/qemu/qemu/commit/a83bddd60de0dfdbc04c6683c2701682073af5cf
  Author: Dongxue Zhang <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips/translate.c: Update OPC_SYNCI

Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved
in the same TB of the store instruction.

Signed-off-by: Dongxue Zhang <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
address@hidden: update microMIPS SYNCI as well]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b231c103afced2eb27af9b6a771ab4b250afb93f
      
https://github.com/qemu/qemu/commit/b231c103afced2eb27af9b6a771ab4b250afb93f
  Author: Yongbok Kim <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix broken MIPS16 and microMIPS

Commit 240ce26a broke MIPS16 and microMIPS support as it didn't
care those branches and jumps don't have delay slot in
MIPS16 and microMIPS.

This patch introduces a new argument delayslot_size to the
gen_compute_branch() indicating size of delay slot {0, 2, 4}.
And the information is used to call handle_delay_slot() forcingly
when no delay slot is required.

There are some microMIPS branch and jump instructions that requires
exact size of instruction in the delay slot. For indicating
these instructions, MIPS_HFLAG_BDS_STRICT flag is introduced.

Those fictional branch opcodes defined to support MIPS16 and
microMIPS are no longer needed.

Signed-off-by: Yongbok Kim <address@hidden>
Tested-by: Jonas Gorski <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
address@hidden: cosmetic changes]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3414e93eb7fcc8d24500edbeddf94b1bd75ac46b
      
https://github.com/qemu/qemu/commit/3414e93eb7fcc8d24500edbeddf94b1bd75ac46b
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()

The function get_DSPControl_24() is unused; remove it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b808a1a812a15b91ccea3a10eea195da65909c5f
      
https://github.com/qemu/qemu/commit/b808a1a812a15b91ccea3a10eea195da65909c5f
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips/op_helper.c: Remove unused do_lbu() function

The do_lbu() function defined by the expansion of HELPER_LD() is
never used, so don't define it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: c7986fd6cd766d95496805a75397c855cb7845af
      
https://github.com/qemu/qemu/commit/c7986fd6cd766d95496805a75397c855cb7845af
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips/translate.c: Add ifdef guard around check_mips64()

The function check_mips64() is only used if TARGET_MIPS64 is defined;
add an ifdef guard to its definition to avoid warnings about it being
unused in other configurations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 31efecccce53ead3197ce42c408033c5689499bb
      
https://github.com/qemu/qemu/commit/31efecccce53ead3197ce42c408033c5689499bb
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips/dsp_helper.c: Add ifdef guards around various functions

Add ifdef TARGET_MIPS64 guards around various functions that are only
called from helpers for TARGET_MIPS64 CPUs; this avoids compiler
warnings when building other configs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 340fff722d8a7cf9c0d4f1e1b4fad03a145a9657
      
https://github.com/qemu/qemu/commit/340fff722d8a7cf9c0d4f1e1b4fad03a145a9657
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-14 (Tue, 14 Oct 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX

Remove the functions gen_load_ACX and gen_store_ACX, which appear to have
been unused since they were first introduced many years ago. These functions
were the only places using the cpu_ACX[] array of TCG globals, so remove
that and its accompanying regnames_ACX[] as well.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 31cc9514a50d1dc9fc71aec4e309c8af6fd83f3e
      
https://github.com/qemu/qemu/commit/31cc9514a50d1dc9fc71aec4e309c8af6fd83f3e
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-22 (Wed, 22 Oct 2014)

  Changed paths:
    M disas/mips.c
    M fpu/softfloat.c
    M hw/mips/mips_malta.c
    M include/fpu/softfloat.h
    M target-mips/cpu.h
    M target-mips/dsp_helper.c
    M target-mips/helper.h
    M target-mips/mips-defs.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141015' into staging

* remotes/lalrae/tags/mips-20141015: (28 commits)
  target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX
  target-mips/dsp_helper.c: Add ifdef guards around various functions
  target-mips/translate.c: Add ifdef guard around check_mips64()
  target-mips/op_helper.c: Remove unused do_lbu() function
  target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()
  target-mips: fix broken MIPS16 and microMIPS
  target-mips/translate.c: Update OPC_SYNCI
  target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA
  mips_malta: update malta's pseudo-bootloader - replace JR with JALR
  target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions
  target-mips: do not allow Status.FR=0 mode in 64-bit FPU
  target-mips: add new Floating Point Comparison instructions
  target-mips: add new Floating Point instructions
  softfloat: add functions corresponding to IEEE-2008 min/maxNumMag
  target-mips: add AUI, LSA and PCREL instruction families
  target-mips: add compact and CP1 branches
  target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions
  target-mips: Status.UX/SX/KX enable 32-bit address wrapping
  target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6
  target-mips: redefine Integer Multiply and Divide instructions
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/01a2050fa5fb...31cc9514a50d
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