[Qemu-commits] [qemu/qemu] 82c39f: target-arm: Add missing 'static' attribute

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 82c39f6a8898b028515eddcdbc4ae50959d0af5d
      
https://github.com/qemu/qemu/commit/82c39f6a8898b028515eddcdbc4ae50959d0af5d
  Author: Stefan Weil <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add missing 'static' attribute

Signed-off-by: Stefan Weil <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6df99dec9e81838423d723996e96236693fa31fe
      
https://github.com/qemu/qemu/commit/6df99dec9e81838423d723996e96236693fa31fe
  Author: Sergey Sorokin <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Break the TB after ISB to execute self-modified code correctly

If any store instruction writes the code inside the same TB
after this store insn, the execution of the TB must be stopped
to execute new code correctly.
As described in ARMv8 manual D3.4.6 self-modifying code must do an
IC invalidation to be valid, and an ISB after it. So it's enough to end
the TB after ISB instruction on the code translation.
Also this TB break is necessary to take any pending interrupts immediately
after an ISB (as required by ARMv8 ARM D1.14.4).

Signed-off-by: Sergey Sorokin <address@hidden>
[PMM: tweaked commit message and comments slightly]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2cde031f5a34996bab32571a26b1a6bcf3e5b5d9
      
https://github.com/qemu/qemu/commit/2cde031f5a34996bab32571a26b1a6bcf3e5b5d9
  Author: Sergey Sorokin <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL

It is incorrect to call arm_el_is_aa64() function for unimplemented EL.
This patch fixes several attempts to do so.

Signed-off-by: Sergey Sorokin <address@hidden>
[PMM: Reworked several of the comments to be more verbose.]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bab27ea2e3855b6495a743f19b9d28cb013443ea
      
https://github.com/qemu/qemu/commit/bab27ea2e3855b6495a743f19b9d28cb013443ea
  Author: Andrew Jones <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: smbios: inform guest of kvm

ARM/AArch64 KVM guests don't have any way to identify
themselves as KVM guests (x86 guests use a CPUID leaf). Now, we
could discuss all sorts of reasons why guests shouldn't need to
know that, but then there's always some case where it'd be
nice... Anyway, now that we have SMBIOS tables in ARM guests,
it's easy for the guest to know that it's a QEMU instance. This
patch takes that one step further, also identifying KVM, when
appropriate. Again, we could debate why generally nothing
should care whether it's of type QEMU or QEMU/KVM, but again,
sometimes it's nice to know...

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Wei Huang <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1424ca8d4320427c3e93722b65e19077969808a2
      
https://github.com/qemu/qemu/commit/1424ca8d4320427c3e93722b65e19077969808a2
  Author: Davorin Mista <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs

Added oslar_write function to OSLAR_EL1 sysreg, using a status variable
in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked
to the newly added read-only OSLSR_EL1 register.

Linux reads from this register during its suspend/resume procedure.

Signed-off-by: Davorin Mista <address@hidden>
[PMM: folded a long line and tweaked a comment]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ad1e8db894fa055ffa9447a5d86520ef1cbac6e9
      
https://github.com/qemu/qemu/commit/ad1e8db894fa055ffa9447a5d86520ef1cbac6e9
  Author: Ryo ONODERA <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M hw/arm/collie.c
    M hw/arm/spitz.c
    M hw/arm/tosa.c

  Log Message:
  -----------
  target-arm: Provide model numbers for Sharp PDAs

* For Collie, Akita, Spitz, Borzoi, Terrier and Tosa PDAs, provide
  model numbers and manufacturer (Sharp) information.

Signed-off-by: Ryo ONODERA <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b64d64de1a5b88de88146e3ad36e7b09b97837eb
      
https://github.com/qemu/qemu/commit/b64d64de1a5b88de88146e3ad36e7b09b97837eb
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M hw/arm/imx25_pdk.c
    M tests/ds1338-test.c

  Log Message:
  -----------
  arm: imx25-pdk: Fix machine name

ARM uses dashes instead of underscores for machine names. Fix imx25_pdk
which has not seen a release yet (so there is no legacy yet).

Cc: Jean-Christophe Dubois <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: Added change to tests/ds1338-test.c to use new machine name]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c209b0537203c58a051e5d837320335cea23e494
      
https://github.com/qemu/qemu/commit/c209b0537203c58a051e5d837320335cea23e494
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  misc: zynq_slcr: Fix MMIO writes

The /4 for offset calculation in MMIO writes was happening twice giving
wrong write offsets. Fix.

While touching the code, change the if-else to be a short returning if
and convert the debug message to a GUEST_ERROR, which is more accurate
for this condition.

Cc: address@hidden
Cc: Guenter Roeck <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14cc7b54372995a6ba72c7719372e4f710fc9b5a
      
https://github.com/qemu/qemu/commit/14cc7b54372995a6ba72c7719372e4f710fc9b5a
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add MDCR_EL2

Add the MDCR_EL2 register. We don't implement any of
the debug-related traps this register controls yet, so
currently it simply reads back as written.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tweaked commit message; moved non-dummy definition from
debug_cp_reginfo to el2_cp_reginfo.]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 74de8c356844080fcabc3a44b08b9d22feda691f
      
https://github.com/qemu/qemu/commit/74de8c356844080fcabc3a44b08b9d22feda691f
  Author: Alexander Gordeev <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Allow zero address for PCI IO space

Currently PCI IO address 0 is not allowed even though
the IO space starts from 0. This update makes  PCI IO
address 0 usable.

CC: Peter Maydell <address@hidden>
CC: Andrew Jones <address@hidden>
Signed-off-by: Alexander Gordeev <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81669b8b81eb450d7b89ee5fdd57bdb73d87022d
      
https://github.com/qemu/qemu/commit/81669b8b81eb450d7b89ee5fdd57bdb73d87022d
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: implement arm_debug_target_el()

Implement debug exception routing according to ARM ARM D2.3.1 Pseudocode
description of routing debug exceptions.

Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e63a2d4d9ed73e33a0b7483085808048be8bbcb1
      
https://github.com/qemu/qemu/commit/e63a2d4d9ed73e33a0b7483085808048be8bbcb1
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Fix GDB breakpoint handling

GDB breakpoints have higher priority so they have to be checked first.
Should GDB breakpoint match, just return from the debug exception
handler.

Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d98bf8f38c17a348ab6e8af196088cd4953acd0
      
https://github.com/qemu/qemu/commit/5d98bf8f38c17a348ab6e8af196088cd4953acd0
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-10-16 (Fri, 16 Oct 2015)

  Changed paths:
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix CPU breakpoint handling

A QEMU breakpoint match is not definitely an architectural breakpoint
match. If an exception is generated unconditionally during translation,
it is hardly possible to ignore it in the debug exception handler.

Generate a call to a helper to check CPU breakpoints and raise an
exception only if any breakpoint matches architecturally.

Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6d57410a79d51d92673c54f26624b44f27fa6214
      
https://github.com/qemu/qemu/commit/6d57410a79d51d92673c54f26624b44f27fa6214
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-17 (Sat, 17 Oct 2015)

  Changed paths:
    M hw/arm/collie.c
    M hw/arm/imx25_pdk.c
    M hw/arm/spitz.c
    M hw/arm/tosa.c
    M hw/arm/virt.c
    M hw/misc/zynq_slcr.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M tests/ds1338-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151016' 
into staging

target-arm queue:
 * break TBs after ISB instructions
 * more support code for future implementation of EL2 and 64-bit EL3
 * tell guest if KVM is enabled in SMBIOS version string
 * implement OSLAR/OSLSR system registers
 * provide better help text for Sharp PDA machine names
 * rename imx25_pdk to imx25-pdk (since it has never been released
   with the underscore-version name)
 * fix MMIO writes in zynq_slcr
 * implement MDCR_EL2
 * virt: allow the guest to configure PCI BARs with zero PCI addresses
 * fix breakpoint handling code

# gpg: Signature made Fri 16 Oct 2015 14:56:15 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20151016:
  target-arm: Fix CPU breakpoint handling
  target-arm: Fix GDB breakpoint handling
  target-arm: implement arm_debug_target_el()
  hw/arm/virt: Allow zero address for PCI IO space
  target-arm: Add MDCR_EL2
  misc: zynq_slcr: Fix MMIO writes
  arm: imx25-pdk: Fix machine name
  target-arm: Provide model numbers for Sharp PDAs
  target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
  hw/arm/virt: smbios: inform guest of kvm
  target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL
  target-arm: Break the TB after ISB to execute self-modified code correctly
  target-arm: Add missing 'static' attribute

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9c1f5bbc739f...6d57410a79d5