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[Qemu-commits] [qemu/qemu] 70f897: tcg/ppc: Adjust exit_tb for change in

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 70f897: tcg/ppc: Adjust exit_tb for change in prologue pla...
Date: Thu, 22 Oct 2015 11:00:07 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 70f897bdc4ce4101ec008317d43090f532bfb07d
      
https://github.com/qemu/qemu/commit/70f897bdc4ce4101ec008317d43090f532bfb07d
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/ppc/tcg-target.c

  Log Message:
  -----------
  tcg/ppc: Adjust exit_tb for change in prologue placement

Changing the prologue to the beginning of the code_gen_buffer
changes the direction of the "return" branch.  Need to change
the logic to match.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5bfd75a35c11dd3aa61c73d0d2cd88137c31519c
      
https://github.com/qemu/qemu/commit/5bfd75a35c11dd3aa61c73d0d2cd88137c31519c
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/ppc/tcg-target.c
    M translate-all.c

  Log Message:
  -----------
  tcg/ppc: Revise goto_tb implementation

Restrict the size of code_gen_buffer to 2GB on ppc64, which
lets us assert that everything is reachable with addis+addi
from tb_ret_addr.  This lets us use a max of 4 insns for goto_tb
instead of 7.

Emit the indirect branch portion of goto_tb up front, which
means we only have to update two insns to update any link.
With a 64-bit store, we can update the link atomically, which
may be required in future.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1e1df962e325e18a5188c4814cd1a10215a48f79
      
https://github.com/qemu/qemu/commit/1e1df962e325e18a5188c4814cd1a10215a48f79
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/ppc/tcg-target.c

  Log Message:
  -----------
  tcg/ppc: Prefer mask over andi.

Prefer the instruction that isn't required to modify cr0.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: c0e40dbdcc291c85faa289a53be60b7b1b7c7598
      
https://github.com/qemu/qemu/commit/c0e40dbdcc291c85faa289a53be60b7b1b7c7598
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/tcg-opc.h

  Log Message:
  -----------
  tcg-opc.h: Simplify insn_start def

We already have a TLADDR_ARGS definition, so rearrange the order
slightly and use it in the definition of insn_start, instead of
having an #ifdef.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: d76f36535099b5d3d880c5e3ac1d411420c8a086
      
https://github.com/qemu/qemu/commit/d76f36535099b5d3d880c5e3ac1d411420c8a086
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M disas/mips.c

  Log Message:
  -----------
  disas/mips: Add R6 jr/jr.hb to disassembler

MIPS r6 encodes jr as jalr zero, and jr.hb as jalr.hb zero, so add these
encodings to the MIPS disassembly table.

Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: ce14bd4d469f3a14f6cbfceb6360aee066a60d72
      
https://github.com/qemu/qemu/commit/ce14bd4d469f3a14f6cbfceb6360aee066a60d72
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/mips/tcg-target.h

  Log Message:
  -----------
  tcg/mips: Add use_mips32r6_instructions definition

Add definition use_mips32r6_instructions to the MIPS TCG backend which
is constant 1 when built for MIPS release 6. This will be used to decide
between pre-R6 and R6 instruction encodings.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: 6e0d096989be52c2b945fc83a9bd15d887bbdb47
      
https://github.com/qemu/qemu/commit/6e0d096989be52c2b945fc83a9bd15d887bbdb47
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/mips/tcg-target.c

  Log Message:
  -----------
  tcg/mips: Support r6 JR encoding

MIPSr6 encodes JR as JALR with zero as the link register, and the pre-r6
JR encoding is removed. Update TCG to use the new encoding when built
for r6.

We still use the old encoding for pre-r6, so as not to confuse return
prediction stack hardware which may detect only particular encodings of
the return instruction.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: bc6d0c22b09a72897d9db4482076f89e7de97400
      
https://github.com/qemu/qemu/commit/bc6d0c22b09a72897d9db4482076f89e7de97400
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/mips/tcg-target.c
    M tcg/mips/tcg-target.h

  Log Message:
  -----------
  tcg/mips: Support r6 multiply/divide encodings

MIPSr6 adds several new integer multiply, divide, and modulo
instructions, and removes several pre-r6 encodings, along with the HI/LO
registers which were the implicit operands of some of those
instructions. Update TCG to use the new instructions when built for r6.

The new instructions actually map much more directly to the TCG ops, as
they only provide a single 32-bit half of the result and in a normal
general purpose register instead of HI or LO.

The mulu2_i32 and muls2_i32 operations are no longer appropriate for r6,
so they are removed from the TCG opcode table. This is because they
would need to emit two separate host instructions anyway (for the high
and low half of the result), which TCG can arrange automatically for us
in the absense of mulu2_i32/muls2_i32 by splitting it into mul_i32 and
mul*h_i32 TCG ops.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: 137d63902faf4960081856db9242cbaf234a23af
      
https://github.com/qemu/qemu/commit/137d63902faf4960081856db9242cbaf234a23af
  Author: James Hogan <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M tcg/mips/tcg-target.c

  Log Message:
  -----------
  tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ

Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).

Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
semantics:
 rd = [!]rt ? rs : rd

The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
 rd = [!]rt ? rs : 0

First we ensure that if one of the movcond input values is zero that it
comes last (we can swap the input arguments if we invert the condition).
This is so that it can exactly match one of the SELNEZ/SELEQZ
instructions and avoid the need to emit the other one.

Otherwise we emit the opposite instruction first into a temporary
register, and OR that into the result:
 SELNEZ/SELEQZ  TMP1, v2, c1
 SELEQZ/SELNEZ  ret, v1, c1
 OR             ret, ret, TMP1

Which does the following:
 ret = cond ? v1 : v2

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>


  Commit: 89a82cd4b6a90fe117fa715e2abe51d5c607560c
      
https://github.com/qemu/qemu/commit/89a82cd4b6a90fe117fa715e2abe51d5c607560c
  Author: Richard Henderson <address@hidden>
  Date:   2015-10-19 (Mon, 19 Oct 2015)

  Changed paths:
    M cpu-exec.c
    M include/qemu/log.h
    M qemu-log.c

  Log Message:
  -----------
  cpu-exec: Add "nochain" debug flag

Respect it to avoid linking TBs together.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6a6739de510706e1d337180d12be74ebbd0c7666
      
https://github.com/qemu/qemu/commit/6a6739de510706e1d337180d12be74ebbd0c7666
  Author: Peter Maydell <address@hidden>
  Date:   2015-10-22 (Thu, 22 Oct 2015)

  Changed paths:
    M cpu-exec.c
    M disas/mips.c
    M include/qemu/log.h
    M qemu-log.c
    M tcg/mips/tcg-target.c
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target.c
    M tcg/tcg-opc.h
    M translate-all.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151021' into staging

Collected tcg backend patches

# gpg: Signature made Wed 21 Oct 2015 22:34:28 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"

* remotes/rth/tags/pull-tcg-20151021:
  cpu-exec: Add "nochain" debug flag
  tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ
  tcg/mips: Support r6 multiply/divide encodings
  tcg/mips: Support r6 JR encoding
  tcg/mips: Add use_mips32r6_instructions definition
  disas/mips: Add R6 jr/jr.hb to disassembler
  tcg-opc.h: Simplify insn_start def
  tcg/ppc: Prefer mask over andi.
  tcg/ppc: Revise goto_tb implementation
  tcg/ppc: Adjust exit_tb for change in prologue placement

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b803894e2c4d...6a6739de5107
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