[Qemu-commits] [qemu/qemu] 235ea1: target-arm: Give CPSR setting on 32-bit exception ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 235ea1f5c89abf30e452539b973b0dbe43d3fe2b
      
https://github.com/qemu/qemu/commit/235ea1f5c89abf30e452539b973b0dbe43d3fe2b
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Give CPSR setting on 32-bit exception return its own helper

The rules for setting the CPSR on a 32-bit exception return are
subtly different from those for setting the CPSR via an instruction
like MSR or CPS. (In particular, in Hyp mode changing the mode bits
is not valid via MSR or CPS.) Split the exception-return case into
its own helper for setting CPSR, so we can eventually handle them
differently in the helper function.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 50866ba5a2cfe922aaf3edb79f6eac5b0653477a
      
https://github.com/qemu/qemu/commit/50866ba5a2cfe922aaf3edb79f6eac5b0653477a
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M linux-user/arm/nwfpe/fpa11.h
    M linux-user/main.c
    M linux-user/signal.c
    M target-arm/cpu.h
    M target-arm/gdbstub.c
    M target-arm/helper.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Add write_type argument to cpsr_write()

Add an argument to cpsr_write() to indicate what kind of CPSR
write is being requested, since the exact behaviour should
differ for the different cases.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: f8c88bbcda76d5674e4bb125471371b41d330df8
      
https://github.com/qemu/qemu/commit/f8c88bbcda76d5674e4bb125471371b41d330df8
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Raw CPSR writes should skip checks and bank switching

Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code from all the
callsites which are using CPSRWriteRaw.

This fixes a bug in 32-bit KVM handling where we had forgotten
the "manually set the mode bits" part and could thus potentially
trash the register state if the mode from the last exit to userspace
differed from the mode on this exit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: ae08792301c182bdec48656dee3dce38b3391a1a
      
https://github.com/qemu/qemu/commit/ae08792301c182bdec48656dee3dce38b3391a1a
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M linux-user/main.c
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Use restrictive mask when calling cpsr_write()

When linux-user code is calling cpsr_write(), use a restrictive
mask to ensure we are limiting the set of CPSR bits we update.
In particular, don't allow the mode bits to be changed.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: cb01d3912c8b000ed26d5fe95f6c194b3e3ba7a6
      
https://github.com/qemu/qemu/commit/cb01d3912c8b000ed26d5fe95f6c194b3e3ba7a6
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: In cpsr_write() ignore mode switches from User mode

The only case where we can attempt a cpsr_write() mode switch from
User is from the gdbstub; all other cases are handled in the
calling code (notably translate.c). Architecturally attempts to
alter the mode bits from user mode are simply ignored (and not
treated as a bad mode switch, which in v8 sets CPSR.IL). Make
mode switches from User ignored in cpsr_write() as well, for
consistency.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 52ff951b4f63a29593650a15efdf82f63d6d962d
      
https://github.com/qemu/qemu/commit/52ff951b4f63a29593650a15efdf82f63d6d962d
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add comment about not implementing NSACR.RFR

QEMU doesn't implement the NSACR.RFR bit, which is a permitted
IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8.
Add a comment to bad_mode_switch() to note that this is why
FIQ is always a valid mode regardless of the CPU's Secure state.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: e6c8fc07b4fce0729bb747770756835f4b0ca7f4
      
https://github.com/qemu/qemu/commit/e6c8fc07b4fce0729bb747770756835f4b0ca7f4
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add Hyp mode checks to bad_mode_switch()

We don't actually support Hyp mode yet, but add the correct
checks for it to the bad_mode_switch() function for completeness.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 58ae2d1f037fae1d90eed4522053a85d79edfbec
      
https://github.com/qemu/qemu/commit/58ae2d1f037fae1d90eed4522053a85d79edfbec
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Forbid mode switch to Mon from Secure EL1

In v8 trying to switch mode to Mon from Secure EL1 is an
illegal mode switch. (In v7 this is impossible as all secure
modes except User are at EL3.) We can handle this case by
making a switch to Mon valid only if the current EL is 3,
which then gives the correct answer whether EL3 is AArch32
or AArch64.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 81907a582901671c15be36a63b5063f88f3487e2
      
https://github.com/qemu/qemu/commit/81907a582901671c15be36a63b5063f88f3487e2
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL

In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
 * the mode field is unchanged
 * PSTATE.IL is set (so any subsequent instructions will UNDEF)
 * any other CPSR fields are written to as normal

This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: af393ffc6da116b9dd4c70901bad1f4cafb1773d
      
https://github.com/qemu/qemu/commit/af393ffc6da116b9dd4c70901bad1f4cafb1773d
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make mode switches from Hyp via CPS and MRS illegal

Mode switches from Hyp to any other mode via the CPS and MRS
instructions are illegal mode switches (though obviously switching
via exception return is valid).  Add this check to bad_mode_switch().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 10eacda787ac9990dc22d4437b289200c819712c
      
https://github.com/qemu/qemu/commit/10eacda787ac9990dc22d4437b289200c819712c
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1

If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to
NonSecure PL1 modes are illegal mode changes. Implement this check
in bad_mode_switch().

(We don't currently implement HCR.TGE, but this is the only missing
check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the
rest of the HCR.TGE checks can be added later as necessary.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: a8d64e735182cbbb5dcc98f41656b118c45e57cc
      
https://github.com/qemu/qemu/commit/a8d64e735182cbbb5dcc98f41656b118c45e57cc
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix handling of SDCR for 32-bit code

Fix two issues with our implementation of the SDCR:
 * it is only present from ARMv8 onwards
 * it does not contain several of the trap bits present in its 64-bit
   counterpart the MDCR_EL3

Put the register description in the right place so that it does not
get enabled for ARMv7 and earlier, and give it a write function so that
we can mask out the bits which should not be allowed to have an effect
if EL3 is 32-bit.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Sergey Fedorov <address@hidden>
Acked-by: Alistair Francis <address@hidden>


  Commit: 1fce1ba985d9c5c96e5b9709e1356d1814b8fa9e
      
https://github.com/qemu/qemu/commit/1fce1ba985d9c5c96e5b9709e1356d1814b8fa9e
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps

Implement the performance monitor register traps controlled
by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance
registers already have an access function to deal with the
user-enable bit, and the TPM checks can be added there. We
also need a new access function which only implements the
TPM checks for use by the few not-EL0-accessible registers
and by PMUSERENR_EL0 (which is always EL0-readable).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Sergey Fedorov <address@hidden>
Acked-by: Alistair Francis <address@hidden>


  Commit: 09aa3bf382243151e77682b2e89f997349b306d8
      
https://github.com/qemu/qemu/commit/09aa3bf382243151e77682b2e89f997349b306d8
  Author: Wei Huang <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M hw/gpio/pl061.c

  Log Message:
  -----------
  ARM: PL061: Checking register r/w accesses to reserved area

pl061.c emulates two GPIO devices, ARM PL061 and TI Stellaris, which
share the same read/write functions (pl061_read and pl061_write).
However PL061 and Stellaris have different GPIO register definitions
and pl061_read()/pl061_write() doesn't check it. This patch enforces
checking on offset, preventing R/W into the reserved memory area.

Signed-off-by: Wei Huang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a55b53a2f46bc5350ec0c3ae8d0cd82eff95a7e8
      
https://github.com/qemu/qemu/commit/a55b53a2f46bc5350ec0c3ae8d0cd82eff95a7e8
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/raspi.c

  Log Message:
  -----------
  raspi: fix SD card with recent sdhci changes

Recent changes to sdhci broke SD on raspi. This change mirrors
the logic to create the SD card device at the board level.

Signed-off-by: Andrew Baumann <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ed0db8663a269fc42d04c1f78d265621b425b9f8
      
https://github.com/qemu/qemu/commit/ed0db8663a269fc42d04c1f78d265621b425b9f8
  Author: Thomas Huth <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add some missing ARM related header files

Some header files in the include/hw/arm/ directory can be assigned
to entries in the MAINTAINERS file.

Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5c1bc9a234704c3d2001e7751b2d33145202a35f
      
https://github.com/qemu/qemu/commit/5c1bc9a234704c3d2001e7751b2d33145202a35f
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h

  Log Message:
  -----------
  sdhci: Revert "add optional quirk property to disable card insertion/removal 
interrupts"

This reverts commit 723697551a7e926abe7d3c7f2966012b8075143d.

This change was poorly tested on my part. It squelched card insertion
interrupts on reset, but that was not necessary because sdhci_reset()
clears all the registers (via the call to memset), so the subsequent
sdhci_insert_eject_cb() call never sees the card insert interrupt
enabled. However, not calling the insert_eject_cb results in prnsts
remaining 0, when it actually needs to be updated to indicate card
presence and R/O status.

Signed-off-by: Andrew Baumann <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0a7ac9f9e72246ce41dfb101c77a58de607aef7c
      
https://github.com/qemu/qemu/commit/0a7ac9f9e72246ce41dfb101c77a58de607aef7c
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h

  Log Message:
  -----------
  sdhci: add quirk property for card insert interrupt status on Raspberry Pi

This quirk is a workaround for the following hardware behaviour, on
which UEFI (specifically, the bootloader for Windows on Pi2) depends:

1. at boot with an SD card present, the interrupt status/enable
   registers are initially zero
2. upon enabling it in the interrupt enable register, the card insert
   bit in the interrupt status register is immediately set
3. after a subsequent controller reset, the card insert interrupt does
   not fire, even if enabled in the interrupt enable register

Signed-off-by: Andrew Baumann <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d44ec156300a149b386a14d3ab349d3b83b66b8c
      
https://github.com/qemu/qemu/commit/d44ec156300a149b386a14d3ab349d3b83b66b8c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW

Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not
having any underlying state. This fixes an issue with booting
KVM enabled kernels when EL2 is on.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e20d84c1407d43d5a2e2ac95dbb46db3b0af8f9f
      
https://github.com/qemu/qemu/commit/e20d84c1407d43d5a2e2ac95dbb46db3b0af8f9f
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF

The v8 ARM ARM defines that unused spaces in the ID_AA64* system
register ranges are Reserved and must RAZ, rather than being UNDEF.
Implement this.

In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2,
and newer versions of the Linux kernel will attempt to read this,
which causes them not to boot up on versions of QEMU missing this fix.

Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6
is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in
the ARMCPU struct so CPUs can override it, though since none do
this too will just RAZ.

Cc: address@hidden
Reported-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>


  Commit: 6e378dd214fbbae8138ff011ec3de7ddf13a445f
      
https://github.com/qemu/qemu/commit/6e378dd214fbbae8138ff011ec3de7ddf13a445f
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-26 (Fri, 26 Feb 2016)

  Changed paths:
    M MAINTAINERS
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/bcm2836.c
    M hw/arm/raspi.c
    M hw/gpio/pl061.c
    M hw/sd/sdhci.c
    M include/hw/sd/sdhci.h
    M linux-user/arm/nwfpe/fpa11.h
    M linux-user/main.c
    M linux-user/signal.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.h
    M target-arm/gdbstub.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160226' 
into staging

target-arm queue:
 * Clean up handling of bad mode switches writing to CPSR, and implement
   the ARMv8 requirement that they set PSTATE.IL
 * Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor
   register accesses
 * Don't implement stellaris-pl061-only registers on generic-pl061
 * Fix SD card handling for raspi
 * Add missing include files to MAINTAINERS
 * Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
 * Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF

# gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160226:
  target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
  target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
  sdhci: add quirk property for card insert interrupt status on Raspberry Pi
  sdhci: Revert "add optional quirk property to disable card insertion/removal 
interrupts"
  MAINTAINERS: Add some missing ARM related header files
  raspi: fix SD card with recent sdhci changes
  ARM: PL061: Checking register r/w accesses to reserved area
  target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
  target-arm: Fix handling of SDCR for 32-bit code
  target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
  target-arm: Make mode switches from Hyp via CPS and MRS illegal
  target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
  target-arm: Forbid mode switch to Mon from Secure EL1
  target-arm: Add Hyp mode checks to bad_mode_switch()
  target-arm: Add comment about not implementing NSACR.RFR
  target-arm: In cpsr_write() ignore mode switches from User mode
  linux-user: Use restrictive mask when calling cpsr_write()
  target-arm: Raw CPSR writes should skip checks and bank switching
  target-arm: Add write_type argument to cpsr_write()
  target-arm: Give CPSR setting on 32-bit exception return its own helper

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/aa53d5bfc35d...6e378dd214fb