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[Qemu-commits] [qemu/qemu] afbee7: ppc: Fix the range check in the LSWI
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[Qemu-commits] [qemu/qemu] afbee7: ppc: Fix the range check in the LSWI instruction |
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Mon, 18 Apr 2016 04:00:03 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: afbee7128c2399b6fca7b744ee560e3a1851118e
https://github.com/qemu/qemu/commit/afbee7128c2399b6fca7b744ee560e3a1851118e
Author: Thomas Huth <address@hidden>
Date: 2016-04-18 (Mon, 18 Apr 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate.c
Log Message:
-----------
ppc: Fix the range check in the LSWI instruction
There are two issues: First, the number of registers that are used has
to be calculated with "(nb + 3) / 4" (i.e. round always up, not down).
Second, the "start <= ra && (start + nr - 32) > ra" condition for the
wrap-around case is wrong: It has to be tested with "||" instead of "&&".
Since we can reuse this check later for the LSWX instruction, let's
place the fixed code into a helper function, too.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 537d3e8e6beea9a0fbd6469eb38450e718244dad
https://github.com/qemu/qemu/commit/537d3e8e6beea9a0fbd6469eb38450e718244dad
Author: Thomas Huth <address@hidden>
Date: 2016-04-18 (Mon, 18 Apr 2016)
Changed paths:
M target-ppc/mem_helper.c
Log Message:
-----------
ppc: Fix the bad exception NIP value and the range check in LSWX
The range checks in the LSWX instruction are completely insufficient:
They do not take the wrap-around case into account, and the check
"reg < rx" should be "reg <= rx" instead. Fix it by using the new
lsw_reg_in_range() helper function that is already used for LSWI, too.
Then there is a second problem: In case the INVAL exception is generated,
the NIP value is wrong, it currently points to the instruction before
the LSWX instruction. This is because gen_lswx() already decreases the
NIP value by 4 (to be prepared for page fault exceptions), and
powerpc_excp() later decreases it again by 4 while handling the program
exception. So to get this right, we've got to undo the "- 4" from
gen_lswx() here before calling helper_raise_exception_err().
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: aa378598fea819b15c00d48048bedfa0dc631132
https://github.com/qemu/qemu/commit/aa378598fea819b15c00d48048bedfa0dc631132
Author: Thomas Huth <address@hidden>
Date: 2016-04-18 (Mon, 18 Apr 2016)
Changed paths:
M target-ppc/machine.c
Log Message:
-----------
ppc: Fix migration of the XER register
env->xer only holds the lower bits of the XER register nowadays, the
SO, OV and CA bits are stored in separate variables (see the function
cpu_write_xer() for details). Since the migration code currently only
reads the "xer" variable, the upper bits are lost during migration.
Fix it by using cpu_read_xer() instead.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ba3899507acfaeee4815beee670c1d80f6f18570
https://github.com/qemu/qemu/commit/ba3899507acfaeee4815beee670c1d80f6f18570
Author: Peter Maydell <address@hidden>
Date: 2016-04-18 (Mon, 18 Apr 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/machine.c
M target-ppc/mem_helper.c
M target-ppc/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160418' into
staging
ppc patch queue for 2-16-04-18
Three bugfixe patches for 2.6 here.
* Two for bad implementation of some of the strong load/store
instructions
* One for bad migration of the XER register. This is a regression
from 2.5, cause by a change in the way we represent at XER during
runtime.
# gpg: Signature made Mon 18 Apr 2016 06:17:03 BST using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.6-20160418:
ppc: Fix migration of the XER register
ppc: Fix the bad exception NIP value and the range check in LSWX
ppc: Fix the range check in the LSWI instruction
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/adde0204e4ed...ba3899507acf
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