[Qemu-commits] [qemu/qemu] 04716b: migration: Define VMSTATE_UINT64_2DARRAY

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 04716bc8fd919a0ac1c8c4502250b01eda39dd4a
      
https://github.com/qemu/qemu/commit/04716bc8fd919a0ac1c8c4502250b01eda39dd4a
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M include/migration/vmstate.h

  Log Message:
  -----------
  migration: Define VMSTATE_UINT64_2DARRAY

Define a VMSTATE_UINT64_2DARRAY macro, to go with the ones we
already have for other type sizes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: b355438de52d0782983bf4bdc47936189a0c988b
      
https://github.com/qemu/qemu/commit/b355438de52d0782983bf4bdc47936189a0c988b
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M include/qemu/bitops.h
    M tests/test-bitops.c

  Log Message:
  -----------
  bitops.h: Implement half-shuffle and half-unshuffle ops

A half-shuffle operation takes a word with zeros in the high half:
 0000 0000 0000 0000 ABCD EFGH IJKL MNOP
and spreads the bits out so they are in every other bit of the word:
 0A0B 0C0D 0E0F 0G0H 0I0J 0K0L 0M0N 0O0P
A half-unshuffle performs the reverse operation.

Provide functions in bitops.h which implement these operations
for 32-bit and 64-bit inputs, and add tests for them.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 712058764da29b2908f6fbf56760ca4f15980709
      
https://github.com/qemu/qemu/commit/712058764da29b2908f6fbf56760ca4f15980709
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Define new arm_is_el3_or_mon() function

The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: bd7d00fc50c9960876dd194ebf0c88889b53e765
      
https://github.com/qemu/qemu/commit/bd7d00fc50c9960876dd194ebf0c88889b53e765
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Provide hook to tell GICv3 about changes of security state

The GICv3 CPU interface needs to know when the CPU it is attached
to makes an exception level or mode transition that changes the
security state, because whether it is asserting IRQ or FIQ can change
depending on these things. Provide a mechanism for letting the GICv3
device register a hook to be called on such changes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 15a21fe028d6475e259a6a9d31ca4878cca3dc75
      
https://github.com/qemu/qemu/commit/15a21fe028d6475e259a6a9d31ca4878cca3dc75
  Author: Pavel Fedin <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Add mp-affinity property for ARM CPU class

This allows to override default affinity IDs on a per-machine basis, and
possibility to retrieve IDs will be used by vGICv3 live migration code.

Signed-off-by: Pavel Fedin <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 07e2034d0817b8006ae4eff07d9d67169d52855a
      
https://github.com/qemu/qemu/commit/07e2034d0817b8006ae4eff07d9d67169d52855a
  Author: Pavel Fedin <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    A hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Add state information

Add state information to GICv3 object structure and implement
arm_gicv3_common_reset().

This commit includes accessor functions for the fields which are
stored as bitmaps in uint32_t arrays.

Signed-off-by: Pavel Fedin <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: significantly overhauled:
 * Add missing qom/cpu.h include
 * Remove legacy-only state fields (we can add them later if/when we add
   legacy emulation)
 * Use arrays of uint32_t to store the various distributor bitmaps,
   and provide accessor functions for the various set/test/etc operations
 * Add various missing register offset #defines
 * Accessor macros which combine distributor and redistributor behaviour
   removed
 * Fields in state structures renamed to match architectural register names
 * Corrected the reset value for GICR_IENABLER0 since we don't support
   legacy mode
 * Added ARM_LINUX_BOOT_IF interface for "we are directly booting a kernel in
   non-secure" so that we can fake up the firmware-mandated reconfiguration
   only when we need it
]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>


  Commit: 3faf2b0cd5451c452fdaab32f9d2fb870b084f80
      
https://github.com/qemu/qemu/commit/3faf2b0cd5451c452fdaab32f9d2fb870b084f80
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure

Move the GICv3 parent_irq and parent_fiq pointers into the
GICv3CPUState structure rather than giving them their own array.
This will make it easy to assert the IRQ and FIQ lines for a
particular CPU interface without having to know or calculate
the CPU index for the GICv3CPUState we are working on.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 757caeed7600028562d5017b93bf2ac2197d0e1c
      
https://github.com/qemu/qemu/commit/757caeed7600028562d5017b93bf2ac2197d0e1c
  Author: Pavel Fedin <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Add vmstate descriptors

Add state structure descriptors for the GICv3 state. We mark
the KVM GICv3 device as having a migration blocker until the
code to save and restore the state in the kernel is implemented.

Signed-off-by: Pavel Fedin <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: Adjust to renamed struct fields; switched to using uint32_t
 array backed bitmaps; add migration blocker setting]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 56992670a45aa14637dafc145e9f9b68172efb13
      
https://github.com/qemu/qemu/commit/56992670a45aa14637dafc145e9f9b68172efb13
  Author: Shlomo Pongratz <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3.c
    M hw/intc/gicv3_internal.h
    A include/hw/intc/arm_gicv3.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: ARM GICv3 device framework

This patch includes the device class itself, some ID register
value functions which will be needed by both distributor
and redistributor, and some skeleton functions for handling
interrupts coming in and going out, which will be filled in
in a subsequent patch.

Signed-off-by: Shlomo Pongratz <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: pulled this patch earlier in the sequence, and left
 some code out of it for a later patch]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>


  Commit: ce187c3c15f4bda579c9833cd78092fb73e651aa
      
https://github.com/qemu/qemu/commit/ce187c3c15f4bda579c9833cd78092fb73e651aa
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: e52af5134035b0fa6d257f68456f6fa8655c86d3
      
https://github.com/qemu/qemu/commit/e52af5134035b0fa6d257f68456f6fa8655c86d3
  Author: Shlomo Pongratz <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3_dist.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement GICv3 distributor registers

Implement the distributor registers of a GICv3.

Signed-off-by: Shlomo Pongratz <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: significantly overhauled/rewritten:
 * use the new bitmap data structures
 * restructure register read/write to handle different width accesses
   natively, since almost all registers are 32-bit only, rather
   than implementing everything as byte accesses
 * implemented security extension support
]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cec93a938a7e84477be0be3ea428717f44dd5f1d
      
https://github.com/qemu/qemu/commit/cec93a938a7e84477be0be3ea428717f44dd5f1d
  Author: Shlomo Pongratz <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement GICv3 redistributor registers

Implement the redistributor registers of a GICv3.

Signed-off-by: Shlomo Pongratz <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: significantly overhauled/rewritten:
 * use the new data structures
 * restructure register read/write to handle different width accesses
   natively, since almost all registers are 32-bit only, rather
   than implementing everything as byte accesses
 * implemented security extension support
]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 287c181ae4132d7cc75ea422051f2c90e90b6493
      
https://github.com/qemu/qemu/commit/287c181ae4132d7cc75ea422051f2c90e90b6493
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions

Wire up the MMIO functions exposed by the distributor and the
redistributor into MMIO regions exposed by the GICv3 device.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: c84428b33fc2d88f17c3f599a9e5d17ae23422c1
      
https://github.com/qemu/qemu/commit/c84428b33fc2d88f17c3f599a9e5d17ae23422c1
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement gicv3_set_irq()

Implement the code which updates the GIC state when an interrupt
input into the GIC is asserted.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 359fbe65e01e13f582d3b9103e7c3ec5ac367a18
      
https://github.com/qemu/qemu/commit/359fbe65e01e13f582d3b9103e7c3ec5ac367a18
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    M hw/intc/arm_gicv3.c
    A hw/intc/arm_gicv3_cpuif.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement GICv3 CPU interface registers

Implement the CPU interface registers for the GICv3; these are
CPU system registers, not MMIO registers.

This commit implements all the registers which are simple
accessors for GIC state, but not those which act as interfaces
for acknowledging, dismissing or generating interrupts. (Those
will be added in a later commit.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: f7b9358e2cf12a5eb07f5f9301fdadc932f9ee03
      
https://github.com/qemu/qemu/commit/f7b9358e2cf12a5eb07f5f9301fdadc932f9ee03
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement gicv3_cpuif_update()

Implement the gicv3_cpuif_update() function which deals with correctly
asserting IRQ and FIQ based on the current running priority of the CPU,
the priority of the highest priority pending interrupt and the CPU's
current exception level and security state.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: b1a0eb777d9304ad69c577d5fdd8e20e4bf5644f
      
https://github.com/qemu/qemu/commit/b1a0eb777d9304ad69c577d5fdd8e20e4bf5644f
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers

Implement the registers in the GICv3 CPU interface which generate
new SGI interrupts.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 227a8653669a8526dcef1020982628282f44820d
      
https://github.com/qemu/qemu/commit/227a8653669a8526dcef1020982628282f44820d
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/gicv3_internal.h
    M trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3: Add IRQ handling CPU interface registers

Add the CPU interface registers which deal with acknowledging
and dismissing interrupts.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 5de8229db542ab7a06e7355e7a095478cc73653a
      
https://github.com/qemu/qemu/commit/5de8229db542ab7a06e7355e7a095478cc73653a
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm/machine.c: Allow user to request GICv3 emulation

Now we have an emulated GICv3, remove the restriction in
gicv3_class_name() so that the user can request a GICv3 with
-machine gic-version=3 even when not using KVM.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 3b1a2225010b1f25745ed6e934cb4c25eb28282e
      
https://github.com/qemu/qemu/commit/3b1a2225010b1f25745ed6e934cb4c25eb28282e
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M target-arm/monitor.c

  Log Message:
  -----------
  target-arm/monitor.c: Advertise emulated GICv3 in capabilities

Now we have an emulated GICv3 we should advertise it via the
capabilities in the monitor protocol.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden


  Commit: 1d3e65aa7ac5afb6798c222abd923eff49ac55f0
      
https://github.com/qemu/qemu/commit/1d3e65aa7ac5afb6798c222abd923eff49ac55f0
  Author: Andrew Jeffery <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/timer/aspeed_timer.c
    M include/hw/timer/aspeed_timer.h

  Log Message:
  -----------
  hw/timer: Add value matching support to aspeed_timer

Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
palmetto-bmc machine. Two match registers are provided for each timer.

Signed-off-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f06765a94a31bdd8b65fc83fd91a6c3f8e8a1195
      
https://github.com/qemu/qemu/commit/f06765a94a31bdd8b65fc83fd91a6c3f8e8a1195
  Author: Shannon Zhao <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/acpi-defs.h

  Log Message:
  -----------
  ACPI: ARM: Present GIC version in MADT table

In ACPI 5.1 Errata, it adds GIC version in GIC distributor structure.
This is useful for guest kernel to identify which version GIC hardware
is. Update GIC distributor structure and present GIC version in MADT
table.

Signed-off-by: Shannon Zhao <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 482b61844ae7c6df39df0b48ac90ffbc87bed7d2
      
https://github.com/qemu/qemu/commit/482b61844ae7c6df39df0b48ac90ffbc87bed7d2
  Author: Peter Maydell <address@hidden>
  Date:   2016-06-17 (Fri, 17 Jun 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M hw/intc/Makefile.objs
    A hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    A hw/intc/arm_gicv3_cpuif.c
    A hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_kvm.c
    A hw/intc/arm_gicv3_redist.c
    A hw/intc/gicv3_internal.h
    M hw/timer/aspeed_timer.c
    M include/hw/acpi/acpi-defs.h
    A include/hw/intc/arm_gicv3.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/timer/aspeed_timer.h
    M include/migration/vmstate.h
    M include/qemu/bitops.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/machine.c
    M target-arm/monitor.c
    M target-arm/op_helper.c
    M tests/test-bitops.c
    M trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160617' 
into staging

target-arm queue:
 * GICv3 emulation

# gpg: Signature made Fri 17 Jun 2016 15:24:28 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits)
  ACPI: ARM: Present GIC version in MADT table
  hw/timer: Add value matching support to aspeed_timer
  target-arm/monitor.c: Advertise emulated GICv3 in capabilities
  target-arm/machine.c: Allow user to request GICv3 emulation
  hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
  hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
  hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
  hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
  hw/intc/arm_gicv3: Implement gicv3_set_irq()
  hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions
  hw/intc/arm_gicv3: Implement GICv3 redistributor registers
  hw/intc/arm_gicv3: Implement GICv3 distributor registers
  hw/intc/arm_gicv3: Implement functions to identify next pending irq
  hw/intc/arm_gicv3: ARM GICv3 device framework
  hw/intc/arm_gicv3: Add vmstate descriptors
  hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
  hw/intc/arm_gicv3: Add state information
  target-arm: Add mp-affinity property for ARM CPU class
  target-arm: Provide hook to tell GICv3 about changes of security state
  target-arm: Define new arm_is_el3_or_mon() function
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/da838dfc40cb...482b61844ae7