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[Qemu-commits] [qemu/qemu] 1ceca9: target-sparc: ignore MMU-faults if MM
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Subject: |
[Qemu-commits] [qemu/qemu] 1ceca9: target-sparc: ignore MMU-faults if MMU is disabled... |
Date: |
Thu, 19 Jan 2017 11:30:03 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 1ceca928538a3633b74a7dc718a05ce6767f2f76
https://github.com/qemu/qemu/commit/1ceca928538a3633b74a7dc718a05ce6767f2f76
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode
while IMMU/DMMU is disabled
- ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor
- signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: c9b459aab8c5775a21dd913fc8820b736181e7be
https://github.com/qemu/qemu/commit/c9b459aab8c5775a21dd913fc8820b736181e7be
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/translate.c
Log Message:
-----------
target-sparc: store cpu super- and hypervisor flags in TB
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 20395e63375358bf6dd147057aaf998abf7abdb9
https://github.com/qemu/qemu/commit/20395e63375358bf6dd147057aaf998abf7abdb9
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: use explicit mmu register pointers
Use explicit register pointers while accessing D/I-MMU registers.
Call cpu_unassigned_access on access to missing registers.
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: c2c7f864df16ed6ef7ef21d255c5593dbeaec261
https://github.com/qemu/qemu/commit/c2c7f864df16ed6ef7ef21d255c5593dbeaec261
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
Log Message:
-----------
target-sparc: add UA2005 TTE bit #defines
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 5b5352b2f41e460f213a515e087c24dac1322f49
https://github.com/qemu/qemu/commit/5b5352b2f41e460f213a515e087c24dac1322f49
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
Log Message:
-----------
target-sparc: add UltraSPARC T1 TLB #defines
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 1a2aefae6627170fdee689b394a65f76080c068a
https://github.com/qemu/qemu/commit/1a2aefae6627170fdee689b394a65f76080c068a
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
Log Message:
-----------
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor
mode
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode
and
PSTATE.ie = 1. At all other times, they are held pending.
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: e4d06ca74b751e486ca2a57f586fd4b858a13085
https://github.com/qemu/qemu/commit/e4d06ca74b751e486ca2a57f586fd4b858a13085
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 4ec3e34654990868ad73a5a452a46d7f9f9dd378
https://github.com/qemu/qemu/commit/4ec3e34654990868ad73a5a452a46d7f9f9dd378
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/asi.h
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: implement UA2005 scratchpad registers
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea
https://github.com/qemu/qemu/commit/b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target-sparc: implement UltraSPARC-T1 Strand status ASR
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 9a10756d1204c3528e47892195349bf882069846
https://github.com/qemu/qemu/commit/9a10756d1204c3528e47892195349bf882069846
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/translate.c
Log Message:
-----------
target-sparc: hypervisor mode takes over nucleus mode
Accordinf to UA2005, 9.3.3 "Address Space Identifiers",
"In hyperprivileged mode, all instruction fetches and loads and stores with
implicit
ASIs use a physical address, regardless of the value of TL".
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 6e040755f12eba34d2fa3d56b18de32d63fea631
https://github.com/qemu/qemu/commit/6e040755f12eba34d2fa3d56b18de32d63fea631
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/int64_helper.c
M target/sparc/win_helper.c
Log Message:
-----------
target-sparc: implement UA2005 hypervisor traps
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: cbc3a6a4cc675516328a2b0d3602355d68b6302d
https://github.com/qemu/qemu/commit/cbc3a6a4cc675516328a2b0d3602355d68b6302d
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/helper.h
M target/sparc/int64_helper.c
M target/sparc/translate.c
M target/sparc/win_helper.c
Log Message:
-----------
target-sparc: implement UA2005 GL register
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: f7f17ef75c9c90db63c44d11dc16fc085ca2c474
https://github.com/qemu/qemu/commit/f7f17ef75c9c90db63c44d11dc16fc085ca2c474
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 5c65df364af0a2cc60af318e5a3011ae5fce293a
https://github.com/qemu/qemu/commit/5c65df364af0a2cc60af318e5a3011ae5fce293a
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target-sparc: fix immediate UA2005 traps
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 84f8f5876628963e67f66edde8a71208c4274ac8
https://github.com/qemu/qemu/commit/84f8f5876628963e67f66edde8a71208c4274ac8
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/translate.c
Log Message:
-----------
target-sparc: use direct address translation in hyperprivileged mode
Please note that QEMU doesn't impelement Real->Physical address
translation. The "Real Address" is always the "Physical Address".
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 7cd39ef234a7e2eea45a08cd15f920da5f1ba008
https://github.com/qemu/qemu/commit/7cd39ef234a7e2eea45a08cd15f920da5f1ba008
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: allow priveleged ASIs in hyperprivileged mode
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 2f1b52920205863024cc86007e88557f4c2c898e
https://github.com/qemu/qemu/commit/2f1b52920205863024cc86007e88557f4c2c898e
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: ignore writes to UA2005 CPU mondo queue register
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 4797a6851975c1239df440c5f01d8566e63717bb
https://github.com/qemu/qemu/commit/4797a6851975c1239df440c5f01d8566e63717bb
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: replace the last tlb entry when no free entries left
Implement the behavior described in the chapter 13.9.11 of
UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005:
"If a TLB Data-In replacement is attempted with all TLB
entries locked and valid, the last TLB entry (entry 63) is
replaced."
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 96df2bc99f9bdaf7a2f13550111f219b72b73708
https://github.com/qemu/qemu/commit/96df2bc99f9bdaf7a2f13550111f219b72b73708
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M linux-user/main.c
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
M target/sparc/machine.c
Log Message:
-----------
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 15f746cedc6db2cc8fc7bcfe7692e02263caeeca
https://github.com/qemu/qemu/commit/15f746cedc6db2cc8fc7bcfe7692e02263caeeca
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: implement UA2005 TSB Pointers
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: e5673ee45e4ce57ca8d538cbdfd186189239d31b
https://github.com/qemu/qemu/commit/e5673ee45e4ce57ca8d538cbdfd186189239d31b
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: simplify ultrasparc_tsb_pointer
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 913b5f2827d83b573a23960ae2b15795c9b925cd
https://github.com/qemu/qemu/commit/913b5f2827d83b573a23960ae2b15795c9b925cd
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/mmu_helper.c
Log Message:
-----------
target-sparc: allow 256M sized pages
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 70f44d2f4bce44fa04426def3290306fa8064b91
https://github.com/qemu/qemu/commit/70f44d2f4bce44fa04426def3290306fa8064b91
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: implement auto-demapping for UA2005 CPUs
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: d00a2334433483d1751d94aabdf47985a68010d3
https://github.com/qemu/qemu/commit/d00a2334433483d1751d94aabdf47985a68010d3
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/mmu_helper.c
Log Message:
-----------
target-sparc: add more registers to dump_mmu
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 7dd8c0760ee197420273a7dfeab13bf54f6bbd8d
https://github.com/qemu/qemu/commit/7dd8c0760ee197420273a7dfeab13bf54f6bbd8d
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: implement UA2005 ASI_MMU (0x21)
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 7285fba083de3f14f6e98abb4469173b56da9480
https://github.com/qemu/qemu/commit/7285fba083de3f14f6e98abb4469173b56da9480
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/cpu.h
M target/sparc/ldst_helper.c
Log Message:
-----------
target-sparc: store the UA2005 entries in sun4u format
According to chapter 13.3 of the
UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005,
only the sun4u format is available for data-access loads.
Store UA2005 entries in the sun4u format to simplify processing.
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8
https://github.com/qemu/qemu/commit/3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.
"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"
Integer stores of all sizes are allowed with these ASIs.
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: a0e893039cf2ce0aacbc8959bc4201cdd192986c
https://github.com/qemu/qemu/commit/a0e893039cf2ce0aacbc8959bc4201cdd192986c
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M MAINTAINERS
M hw/timer/Makefile.objs
A hw/timer/sun4v-rtc.c
A include/hw/timer/sun4v-rtc.h
Log Message:
-----------
target-sparc: implement sun4v RTC
Signed-off-by: Artyom Tarasenko <address@hidden>
Commit: fff54d2269de32d09458f86d111eade917137835
https://github.com/qemu/qemu/commit/fff54d2269de32d09458f86d111eade917137835
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M hw/sparc64/Makefile.objs
A hw/sparc64/sparc64.c
M hw/sparc64/sun4u.c
M hw/timer/sun4v-rtc.c
A include/hw/sparc/sparc64.h
Log Message:
-----------
target-sparc: move common cpu initialisation routines to sparc64.c
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: a2664ca0eced57dfc9f261fa1b210f24ddac649d
https://github.com/qemu/qemu/commit/a2664ca0eced57dfc9f261fa1b210f24ddac649d
Author: Artyom Tarasenko <address@hidden>
Date: 2017-01-18 (Wed, 18 Jan 2017)
Changed paths:
M MAINTAINERS
M default-configs/sparc64-softmmu.mak
M hw/sparc64/Makefile.objs
A hw/sparc64/niagara.c
M hw/sparc64/sun4u.c
M qemu-doc.texi
Log Message:
-----------
target-sparc: fix up niagara machine
Remove the Niagara stub implementation from sun4u.c and add a machine,
compatible with Legion simulator from the OpenSPARC T1 project.
The machine uses the firmware supplied with the OpenSPARC T1 project,
http://download.oracle.com/technetwork/systems/opensparc/OpenSPARCT1_Arch.1.5.tar.bz2
in the directory S10image/, and is able to boot the supplied Solaris 10 image.
Note that for compatibility with the naming conventions for SPARC machines
the new machine name is lowercase niagara.
Signed-off-by: Artyom Tarasenko <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 0f6bcf68a99efdc531b209551f2b760b0bdcc554
https://github.com/qemu/qemu/commit/0f6bcf68a99efdc531b209551f2b760b0bdcc554
Author: Peter Maydell <address@hidden>
Date: 2017-01-19 (Thu, 19 Jan 2017)
Changed paths:
M MAINTAINERS
M default-configs/sparc64-softmmu.mak
M hw/sparc64/Makefile.objs
A hw/sparc64/niagara.c
A hw/sparc64/sparc64.c
M hw/sparc64/sun4u.c
M hw/timer/Makefile.objs
A hw/timer/sun4v-rtc.c
A include/hw/sparc/sparc64.h
A include/hw/timer/sun4v-rtc.h
M linux-user/main.c
M qemu-doc.texi
M target/sparc/asi.h
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/helper.h
M target/sparc/int64_helper.c
M target/sparc/ldst_helper.c
M target/sparc/machine.c
M target/sparc/mmu_helper.c
M target/sparc/translate.c
M target/sparc/win_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into
staging
add OpenSPARC T1 emulation
# gpg: Signature made Wed 18 Jan 2017 22:25:47 GMT
# gpg: using RSA key 0x3360C3F7411A125F
# gpg: Good signature from "Artyom Tarasenko <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2AD8 6149 17F4 B2D7 05C0 BB12 3360 C3F7 411A 125F
* remotes/artyom/tags/pull-sun4v-20170118: (30 commits)
target-sparc: fix up niagara machine
target-sparc: move common cpu initialisation routines to sparc64.c
target-sparc: implement sun4v RTC
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
target-sparc: store the UA2005 entries in sun4u format
target-sparc: implement UA2005 ASI_MMU (0x21)
target-sparc: add more registers to dump_mmu
target-sparc: implement auto-demapping for UA2005 CPUs
target-sparc: allow 256M sized pages
target-sparc: simplify ultrasparc_tsb_pointer
target-sparc: implement UA2005 TSB Pointers
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
target-sparc: replace the last tlb entry when no free entries left
target-sparc: ignore writes to UA2005 CPU mondo queue register
target-sparc: allow priveleged ASIs in hyperprivileged mode
target-sparc: use direct address translation in hyperprivileged mode
target-sparc: fix immediate UA2005 traps
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
target-sparc: implement UA2005 GL register
target-sparc: implement UA2005 hypervisor traps
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/5e59fb10ce5e...0f6bcf68a99e
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