[Qemu-commits] [qemu/qemu] 50f110: target/arm: Implement MSR/MRS access

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[Qemu-commits] [qemu/qemu] 50f110: target/arm: Implement MSR/MRS access

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 50f110: target/arm: Implement MSR/MRS access to NS banked ...
Date:	Thu, 21 Sep 2017 10:28:16 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 50f11062d4c896408731d6a286bcd116d1e08465
      
https://github.com/qemu/qemu/commit/50f11062d4c896408731d6a286bcd116d1e08465
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement MSR/MRS access to NS banked registers

In v8M the MSR and MRS instructions have extra register value
encodings to allow secure code to access the non-secure banked
version of various special registers.

(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because
we don't currently implement the stack limit registers at all.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 17906a162a1febef92e1d3eddc090e967a351757
      
https://github.com/qemu/qemu/commit/17906a162a1febef92e1d3eddc090e967a351757
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  nvic: Add banked exception states

For the v8M security extension, some exceptions must be banked
between security states. Add the new vecinfo array which holds
the state for the banked exceptions and migrate it if the
CPU the NVIC is attached to implements the security extension.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e93bc2ac11cd37796fd48e11eaeacec3aff20f9c
      
https://github.com/qemu/qemu/commit/e93bc2ac11cd37796fd48e11eaeacec3aff20f9c
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  nvic: Add cached vectpending_is_s_banked state

With banked exceptions, just the exception number in
s->vectpending is no longer sufficient to uniquely identify
the pending exception. Add a vectpending_is_s_banked bool
which is true if the exception is using the sec_vectors[]
array.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 5255fcf8e47acd059e2f0d414841c40231c1bd22
      
https://github.com/qemu/qemu/commit/5255fcf8e47acd059e2f0d414841c40231c1bd22
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  nvic: Add cached vectpending_prio state

Instead of looking up the pending priority
in nvic_pending_prio(), cache it in a new state struct
field. The calculation of the pending priority given
the interrupt number is more complicated in v8M with
the security extension, so the caching will be worthwhile.

This changes nvic_pending_prio() from returning a full
(group + subpriority) priority value to returning a group
priority. This doesn't require changes to its callsites
because we use it only in comparisons of the form
  execution_prio > nvic_pending_prio()
and execution priority is always a group priority, so
a test (exec prio > full prio) is true if and only if
(execprio > group_prio).

(Architecturally the expected comparison is with the
group priority for this sort of "would we preempt" test;
we were only doing a test with a full priority as an
optimisation to avoid the mask, which is possible
precisely because the two comparisons always give the
same answer.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 3b2e934463121f06d04e4d17658a9a7cdc3717b0
      
https://github.com/qemu/qemu/commit/3b2e934463121f06d04e4d17658a9a7cdc3717b0
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  nvic: Implement AIRCR changes for v8M

The Application Interrupt and Reset Control Register has some changes
for v8M:
 * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have
   real state if the security extension is implemented and otherwise
   are constant
 * the PRIGROUP field is banked between security states
 * non-secure code can be blocked from using the SYSRESET bit
   to reset the system if SYSRESETREQS is set

Implement the new state and the changes to register read and write.
For the moment we ignore the effects of the secure PRIGROUP.
We will implement the effects of PRIS and BFHFNMIS later.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 028b0da424ba85049557c61f9f0a8a6698352b41
      
https://github.com/qemu/qemu/commit/028b0da424ba85049557c61f9f0a8a6698352b41
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Make ICSR.RETTOBASE handle banked exceptions

Update the code in nvic_rettobase() so that it checks the
sec_vectors[] array as well as the vectors[] array if needed.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e1be0a576ba4836e772d717fcc8d3c79e560179b
      
https://github.com/qemu/qemu/commit/e1be0a576ba4836e772d717fcc8d3c79e560179b
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  nvic: Implement NVIC_ITNS<n> registers

For v8M, the NVIC has a new set of registers per interrupt,
NVIC_ITNS<n>. These determine whether the interrupt targets Secure
or Non-secure state. Implement the register read/write code for
these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,
NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure
accesses to fields corresponding to interrupts which are
configured to target secure state.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ff96c64aec91fa2abc134347ad032c50376a6462
      
https://github.com/qemu/qemu/commit/ff96c64aec91fa2abc134347ad032c50376a6462
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events

  Log Message:
  -----------
  nvic: Handle banked exceptions in nvic_recompute_state()

Update the nvic_recompute_state() code to handle the security
extension and its associated banked registers.

Code that uses the resulting cached state (ie the irq
acknowledge and complete code) will be updated in a later
commit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2fb50a33401a2415b71ddc291e8a77bcd2f9e547
      
https://github.com/qemu/qemu/commit/2fb50a33401a2415b71ddc291e8a77bcd2f9e547
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  nvic: Make set_pending and clear_pending take a secure parameter

Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()
functions take a bool indicating whether to pend the secure
or non-secure version of a banked interrupt, and update the
callsites accordingly.

In most callsites we can simply pass the correct security
state in; in a couple of cases we use TODO comments to indicate
that we will return the code in a subsequent commit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e6a0d3500d3a0032680a3eca038c60c5cbab60f8
      
https://github.com/qemu/qemu/commit/e6a0d3500d3a0032680a3eca038c60c5cbab60f8
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events

  Log Message:
  -----------
  nvic: Make SHPR registers banked

Make the set_prio() function take a bool indicating
whether to pend the secure or non-secure version of a banked
interrupt, and use this to implement the correct banking
semantics for the SHPR registers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 80ac2390358c906215a849670ca5b7a3d1d112a3
      
https://github.com/qemu/qemu/commit/80ac2390358c906215a849670ca5b7a3d1d112a3
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Compare group priority for escalation to HF

In armv7m_nvic_set_pending() we have to compare the
priority of an exception against the execution priority
to decide whether it needs to be escalated to HardFault.
In the specification this is a comparison against the
exception's group priority; for v7M we implemented it
as a comparison against the raw exception priority
because the two comparisons will always give the
same answer. For v8M the existence of AIRCR.PRIS and
the possibility of different PRIGROUP values for secure
and nonsecure exceptions means we need to explicitly
calculate the vector's group priority for this check.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 94a34abe32fcdc70b3ee388ccf48b6d3d1aedcfc
      
https://github.com/qemu/qemu/commit/94a34abe32fcdc70b3ee388ccf48b6d3d1aedcfc
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: In escalation to HardFault, support HF not being priority -1

When escalating to HardFault, we must go into Lockup if we
can't take the synchronous HardFault because the current
execution priority is already at or below the priority of
HardFault. In v7M HF is always priority -1 so a simple < 0
comparison sufficed; in v8M the priority of HardFault can
vary depending on whether it is a Secure or NonSecure
HardFault, so we must check against the priority of the
HardFault exception vector we're about to use.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 331f4bae6c514a719676d803625cfe197d81a91c
      
https://github.com/qemu/qemu/commit/331f4bae6c514a719676d803625cfe197d81a91c
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Implement v8M changes to fixed priority exceptions

In v7M, the fixed-priority exceptions are:
 Reset: -3
 NMI: -2
 HardFault: -1

In v8M, this changes because Secure HardFault may need
to be prioritised above NMI:
 Reset: -4
 Secure HardFault if AIRCR.BFHFNMINS == 1: -3
 NMI: -2
 Secure HardFault if AIRCR.BFHFNMINS == 0: -1
 NonSecure HardFault: -1

Make these changes, including support for changing the
priority of Secure HardFault as AIRCR.BFHFNMINS changes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7208b426c7347982af8f5d6f2608cab6b3431ede
      
https://github.com/qemu/qemu/commit/7208b426c7347982af8f5d6f2608cab6b3431ede
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear

If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault
can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually
preempt execution. The simple way to achieve this is to clear the
enable bit for it, since the enable bit isn't guest visible.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 49c80c380d665bcc7d5b68ea1ec3617e51a90d73
      
https://github.com/qemu/qemu/commit/49c80c380d665bcc7d5b68ea1ec3617e51a90d73
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Handle v8M changes in nvic_exec_prio()

Update nvic_exec_prio() to support the v8M changes:
 * BASEPRI, FAULTMASK and PRIMASK are all banked
 * AIRCR.PRIS can affect NS priorities
 * AIRCR.BFHFNMINS affects FAULTMASK behaviour

These changes mean that it's no longer possible to
definitely say that if FAULTMASK is set it overrides
PRIMASK, and if PRIMASK is set it overrides BASEPRI
(since if PRIMASK_NS is set and AIRCR.PRIS is set then
whether that 0x80 priority should take effect or the
priority in BASEPRI_S depends on the value of BASEPRI_S,
for instance). So we switch to the same approach used
by the pseudocode of working through BASEPRI, PRIMASK
and FAULTMASK and overriding the previous values if
needed.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5d4791991d4de12e83d44738417c9e964167b6e8
      
https://github.com/qemu/qemu/commit/5d4791991d4de12e83d44738417c9e964167b6e8
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Handle banking in negative-execution-priority check in 
cpu_mmu_index()

Now that we have a banked FAULTMASK register and banked exceptions,
we can implement the correct check in cpu_mmu_index() for whether
the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes
handlers which have requested a negative execution priority to run
with the MPU disabled. In v8M the test has to check this for the
current security state and so takes account of banking.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 3f1e0eb7c38c19bd2a4bfa8398921d29a1080249
      
https://github.com/qemu/qemu/commit/3f1e0eb7c38c19bd2a4bfa8398921d29a1080249
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Make ICSR banked for v8M

The ICSR NVIC register is banked for v8M. This doesn't
require any new state, but it does mean that some bits
are controlled by BFHNFNMINS and some bits must work
with the correct banked exception. There is also a new
in v8M PENDNMICLR bit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 437d59c17e96976a567ad1547e272cdfe4a5f1d7
      
https://github.com/qemu/qemu/commit/437d59c17e96976a567ad1547e272cdfe4a5f1d7
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Make SHCSR banked for v8M

Handle banking of SHCSR: some register bits are banked between
Secure and Non-Secure, and some are only accessible to Secure.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5cb18069d7b9486126d1d6f08b7ffd28f57a4fa3
      
https://github.com/qemu/qemu/commit/5cb18069d7b9486126d1d6f08b7ffd28f57a4fa3
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  nvic: Support banked exceptions in acknowledge and complete

Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()
to handle banked exceptions:
 * acknowledge needs to use the correct vector, which may be
   in sec_vectors[]
 * acknowledge needs to return to its caller whether the
   exception should be taken to secure or non-secure state
 * complete needs its caller to tell it whether the exception
   being completed is a secure one or not

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4ce31af4aeb8471f6a913de7c59d3bde1fc4f03d
      
https://github.com/qemu/qemu/commit/4ce31af4aeb8471f6a913de7c59d3bde1fc4f03d
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Remove out of date ARM ARM section references in A64 decoder

In the A64 decoder, we have a lot of references to section numbers
from version A.a of the v8A ARM ARM (DDI0487). This version of the
document is now long obsolete (we are currently on revision B.a),
and various intervening versions renumbered all the sections.

The most recent B.a version of the document doesn't assign
section numbers at all to the individual instruction classes
in the way that the various A.x versions did. The simplest thing
to do is just to delete all the out of date C.x.x references.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 7b675f1f971ba8a65711e38c2a2faac4244899c1
      
https://github.com/qemu/qemu/commit/7b675f1f971ba8a65711e38c2a2faac4244899c1
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/arm/palm.c

  Log Message:
  -----------
  hw/arm/palm.c: Don't use old_mmio for static_ops

Update the static_ops functions to use new-style mmio
rather than the legacy old_mmio functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 940caf1f7e91619c58ed909914628d1473f8d9f6
      
https://github.com/qemu/qemu/commit/940caf1f7e91619c58ed909914628d1473f8d9f6
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/gpio/omap_gpio.c

  Log Message:
  -----------
  hw/gpio/omap_gpio.c: Don't use old_mmio

Drop the use of old_mmio in the omap2_gpio memory ops.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 27f5bab84dae6cc808099c32a34ee8868de3229a
      
https://github.com/qemu/qemu/commit/27f5bab84dae6cc808099c32a34ee8868de3229a
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/timer/omap_synctimer.c

  Log Message:
  -----------
  hw/timer/omap_synctimer.c: Don't use old_mmio

Don't use the old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 13dfde3320914042bf804291e685e891298bd001
      
https://github.com/qemu/qemu/commit/13dfde3320914042bf804291e685e891298bd001
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/timer/omap_gptimer.c

  Log Message:
  -----------
  hw/timer/omap_gptimer: Don't use old_mmio

Don't use the old_mmio struct in memory region ops.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 28dc207f5f877fcb2cff43367f7a84a45fdec630
      
https://github.com/qemu/qemu/commit/28dc207f5f877fcb2cff43367f7a84a45fdec630
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/i2c/omap_i2c.c

  Log Message:
  -----------
  hw/i2c/omap_i2c.c: Don't use old_mmio

Don't use old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: fc14cf0e95e8974cb451961391d1ecc626c34407
      
https://github.com/qemu/qemu/commit/fc14cf0e95e8974cb451961391d1ecc626c34407
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/arm/omap2.c

  Log Message:
  -----------
  hw/arm/omap2.c: Don't use old_mmio

Don't use old_mmio in the memory region ops struct.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 96401bad453482c24dd8f9f15a45994d7b99c54b
      
https://github.com/qemu/qemu/commit/96401bad453482c24dd8f9f15a45994d7b99c54b
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/timer/Makefile.objs
    A hw/timer/mss-timer.c
    A include/hw/timer/mss-timer.h

  Log Message:
  -----------
  msf2: Add Smartfusion2 System timer

Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Acked-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0ee1e1f4691cbe5c219be49ac9d0ff4ac4812530
      
https://github.com/qemu/qemu/commit/0ee1e1f4691cbe5c219be49ac9d0ff4ac4812530
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/msf2-sysreg.c
    M hw/misc/trace-events
    A include/hw/misc/msf2-sysreg.h

  Log Message:
  -----------
  msf2: Microsemi Smartfusion2 System Register block

Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Acked-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 268ee7deb4e9bea1c1f9911780f584f71edcf1e0
      
https://github.com/qemu/qemu/commit/268ee7deb4e9bea1c1f9911780f584f71edcf1e0
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/ssi/Makefile.objs
    A hw/ssi/mss-spi.c
    A include/hw/ssi/mss-spi.h

  Log Message:
  -----------
  msf2: Add Smartfusion2 SPI controller

Modelled Microsemi's Smartfusion2 SPI controller.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ebc1fbb4a1400f7c78d38360db5566c6cbfab4c7
      
https://github.com/qemu/qemu/commit/ebc1fbb4a1400f7c78d38360db5566c6cbfab4c7
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/msf2-soc.c
    A include/hw/arm/msf2-soc.h

  Log Message:
  -----------
  msf2: Add Smartfusion2 SoC

Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMD: drop cpu_model to directly use cpu type, check m3clk non null]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6d262dcb7d108eda93813574c2061398084dc795
      
https://github.com/qemu/qemu/commit/6d262dcb7d108eda93813574c2061398084dc795
  Author: Subbaraya Sundeep <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/msf2-som.c

  Log Message:
  -----------
  msf2: Add Emcraft's Smartfusion2 SOM kit

Emulated Emcraft's Smartfusion2 System On Module starter
kit.

Signed-off-by: Subbaraya Sundeep <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMD: drop cpu_model to directly use cpu type]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0a8066f0c068f1e318a1aacd7864fc00e455a37b
      
https://github.com/qemu/qemu/commit/0a8066f0c068f1e318a1aacd7864fc00e455a37b
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-21 (Thu, 21 Sep 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/msf2-soc.c
    A hw/arm/msf2-som.c
    M hw/arm/omap2.c
    M hw/arm/palm.c
    M hw/gpio/omap_gpio.c
    M hw/i2c/omap_i2c.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/trace-events
    M hw/misc/Makefile.objs
    A hw/misc/msf2-sysreg.c
    M hw/misc/trace-events
    M hw/ssi/Makefile.objs
    A hw/ssi/mss-spi.c
    M hw/timer/Makefile.objs
    A hw/timer/mss-timer.c
    M hw/timer/omap_gptimer.c
    M hw/timer/omap_synctimer.c
    A include/hw/arm/msf2-soc.h
    M include/hw/intc/armv7m_nvic.h
    A include/hw/misc/msf2-sysreg.h
    A include/hw/ssi/mss-spi.h
    A include/hw/timer/mss-timer.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170921' 
into staging

target-arm queue:
 * more preparatory work for v8M support
 * convert some omap devices away from old_mmio
 * remove out of date ARM ARM section references in comments
 * add the Smartfusion2 board

# gpg: Signature made Thu 21 Sep 2017 17:40:40 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170921: (31 commits)
  msf2: Add Emcraft's Smartfusion2 SOM kit
  msf2: Add Smartfusion2 SoC
  msf2: Add Smartfusion2 SPI controller
  msf2: Microsemi Smartfusion2 System Register block
  msf2: Add Smartfusion2 System timer
  hw/arm/omap2.c: Don't use old_mmio
  hw/i2c/omap_i2c.c: Don't use old_mmio
  hw/timer/omap_gptimer: Don't use old_mmio
  hw/timer/omap_synctimer.c: Don't use old_mmio
  hw/gpio/omap_gpio.c: Don't use old_mmio
  hw/arm/palm.c: Don't use old_mmio for static_ops
  target/arm: Remove out of date ARM ARM section references in A64 decoder
  nvic: Support banked exceptions in acknowledge and complete
  nvic: Make SHCSR banked for v8M
  nvic: Make ICSR banked for v8M
  target/arm: Handle banking in negative-execution-priority check in 
cpu_mmu_index()
  nvic: Handle v8M changes in nvic_exec_prio()
  nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
  nvic: Implement v8M changes to fixed priority exceptions
  nvic: In escalation to HardFault, support HF not being priority -1
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9ee660e7c138...0a8066f0c068
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