[Qemu-commits] [qemu/qemu] 4d309c: uninorth: trivial style fixups

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[Qemu-commits] [qemu/qemu] 4d309c: uninorth: trivial style fixups

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 4d309c: uninorth: trivial style fixups
Date:	Fri, 27 Apr 2018 03:39:03 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4d309c96635b7a961e3e86e2605a97ef945aeee2
      
https://github.com/qemu/qemu/commit/4d309c96635b7a961e3e86e2605a97ef945aeee2
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: trivial style fixups

This makes sure we keep patchew/checkpatch happy during the remainder of this
patchset.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3e0204e15e93e0358339a0feff8f0ec7fe513e20
      
https://github.com/qemu/qemu/commit/3e0204e15e93e0358339a0feff8f0ec7fe513e20
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: remove second set of uninorth token registers

Commit 593c181160: "PPC: Newworld: Add second uninorth control register set"
added a second set of uninorth registers at 0xf3000000.

Testing MacOS 9.2 to MacOS X 10.4 reveals no accesses to this address and I
can't find any reference to it in Apple's Core99.cpp source so I'm assuming
that this was the result of another bug that has now been fixed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0203459943ebcb366f68ff65f2191c18ee7533d9
      
https://github.com/qemu/qemu/commit/0203459943ebcb366f68ff65f2191c18ee7533d9
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: QOMify PCI and AGP host bridges

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 72941bb76aeeb63d24850bb7fdbb126b7190fd13
      
https://github.com/qemu/qemu/commit/72941bb76aeeb63d24850bb7fdbb126b7190fd13
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: remove stray PCIBus realize from mac_newworld.c

After QOMification this is clearly no longer needed (and possibly hasn't been
for some time).

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5d2eaa02501c9a75a221caa443553d3cc6077cfd
      
https://github.com/qemu/qemu/commit/5d2eaa02501c9a75a221caa443553d3cc6077cfd
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    A include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: move uninorth definitions into uninorth.h

Signed-off-by: Mark Cave-Ayland <address@hidden>
[dwg: Added hw/hw.h #include as suggested by Philippe Mathieu-Daudé]
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0f4b5415c31ed1fee02f5826fe0d2d585806fa95
      
https://github.com/qemu/qemu/commit/0f4b5415c31ed1fee02f5826fe0d2d585806fa95
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth 
device

This is in preparation for moving the device wiring into the New World machine.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a5ed75fe2e6625b2ab9ed0694d7a5c95a74b84f7
      
https://github.com/qemu/qemu/commit/a5ed75fe2e6625b2ab9ed0694d7a5c95a74b84f7
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/intc/heathrow_pic.c
    M hw/ppc/mac.h
    M hw/ppc/mac_oldworld.c
    M include/hw/intc/heathrow_pic.h

  Log Message:
  -----------
  heathrow: remove obsolete heathow_init() function

Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b0318ec10b2a97cac0cdce50a693a11f882c8549
      
https://github.com/qemu/qemu/commit/b0318ec10b2a97cac0cdce50a693a11f882c8549
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/grackle.c
    M hw/ppc/mac.h
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  grackle: general tidy-up and QOMify

This is the first step towards removing the old-style pci_grackle_init()
function. Following on from the previous commit we can now pass the heathrow
device as an object link and wire up the heathrow IRQs via qdev GPIOs.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a773e64a8fd2a3ef97d6e405dbfb28c17660136d
      
https://github.com/qemu/qemu/commit/a773e64a8fd2a3ef97d6e405dbfb28c17660136d
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/grackle.c
    M hw/ppc/mac.h
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  grackle: remove deprecated pci_grackle_init() function

Instead wire up the grackle device inside the Mac Old World machine.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a94e5f998bf353e848a9ae7c679b06fff36b4698
      
https://github.com/qemu/qemu/commit/a94e5f998bf353e848a9ae7c679b06fff36b4698
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/grackle.c
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  grackle: move PCI IO (ISA) memory region into the grackle device

This simplifies the Old World machine to simply mapping the ISA memory region
into the main address space.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ab1244b53d8781e1f2c3dcbdd890afe1b817ca02
      
https://github.com/qemu/qemu/commit/ab1244b53d8781e1f2c3dcbdd890afe1b817ca02
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/mac.h
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly

Introduce constants for the pre-defined Old World IRQs to help keep things
readable.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 20d2514ad88057b8ef400cc4f1484d9160a9781a
      
https://github.com/qemu/qemu/commit/20d2514ad88057b8ef400cc4f1484d9160a9781a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/misc/macio/macio.c
    M hw/ppc/mac_oldworld.c
    M include/hw/misc/macio/macio.h

  Log Message:
  -----------
  mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()

Since the macio device has a link to the PIC device, we can now wire up the
IRQs directly via qdev GPIOs rather than having to use an intermediate array.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 132e9906d64beb8873ca5efe028a052dec6c4550
      
https://github.com/qemu/qemu/commit/132e9906d64beb8873ca5efe028a052dec6c4550
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: move PCI mmio memory region initialisation into init function

Whilst we are here, rename the memory regions to better reflect whether they
belong to either a PCI or an AGP bus.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0b065209549fdd503fe109b09d78500bb05c9f7f
      
https://github.com/qemu/qemu/commit/0b065209549fdd503fe109b09d78500bb05c9f7f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: introduce temporary pic_irqs device property

This is in preparation for moving the PCI bus wiring inside the uninorth
host bridge devices. In the future it will be possible to remove this once the
PICs have been switched to use qdev GPIOs.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 32cde6154cd252bfa23d05f43a165797e2430ff4
      
https://github.com/qemu/qemu/commit/32cde6154cd252bfa23d05f43a165797e2430ff4
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: move PCI host bridge bus initialisation into device realize

Since the IO address space is fixed to use the standard system IO address
space then we can also use the opportunity to remove the address_space_io
parameter from pci_pmac_init() and pci_pmac_u3_init().

Note we also move the default mac99 PCI bus to the end of the initialisation
list so that it becomes the default destination for any devices specified
via -device without an explicit PCI bus provided.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c1d66d378c6dd1f112b753c98a308688dd0af24e
      
https://github.com/qemu/qemu/commit/c1d66d378c6dd1f112b753c98a308688dd0af24e
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: fix PCI and AGP bus mixup

Somewhere in the history of time, the initialisation of the PCI buses for the
AGP and PCI host bridges got mixed up in that the PCI host bridge was
creating an instance of the AGP PCI bus, and the AGP PCI bus was missing.

Swap the PCI host bridge over to use the correct PCI bus (including setting
the kMacRISCPCIAddressSelect register used by MacOS X) and add the missing
reference to the AGP PCI bus.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1ff861d289bf2bef65cb5ef20303583bd72ec930
      
https://github.com/qemu/qemu/commit/1ff861d289bf2bef65cb5ef20303583bd72ec930
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: enable internal PCI host bridge

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7b19318bee746628b8cd9795d7a944c26779d60f
      
https://github.com/qemu/qemu/commit/7b19318bee746628b8cd9795d7a944c26779d60f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: remove obsolete pci_pmac_init() function

Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_unin_main_init().

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8ce3f743c78f422ff87da76553c9421391f3adbf
      
https://github.com/qemu/qemu/commit/8ce3f743c78f422ff87da76553c9421391f3adbf
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  uninorth: remove obsolete pci_pmac_u3_init() function

Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_u3_agp_init().

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e7755cc1142db474bfa47247a92c59996af0502a
      
https://github.com/qemu/qemu/commit/e7755cc1142db474bfa47247a92c59996af0502a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac_newworld.c
    M include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: use object link to pass OpenPIC object to uninorth

Now that the OpenPIC is wired up via the board, we can now remove our temporary
PIC qdev pointer property and replace it with an object link instead.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e226efbb262468241c2c8828373a84ffd93992ac
      
https://github.com/qemu/qemu/commit/e226efbb262468241c2c8828373a84ffd93992ac
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac_newworld.c
    M include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: move PCI IO (ISA) memory region into the uninorth device

Do this for both the uninorth main and uninorth u3 AGP buses, using the main
PCI bus for each machine (this ensures the IO addresses still match those
used by OpenBIOS).

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c90c393c2dca764bf2a062b3769ac0de32f5fe28
      
https://github.com/qemu/qemu/commit/c90c393c2dca764bf2a062b3769ac0de32f5fe28
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c
    M include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: rename UNINState to UNINHostState

The existing UNINState actually represents the PCI/AGP host bridge stage so
rename it accordingly.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a2f04333a340282c0842e76c055297cb7ba56f0f
      
https://github.com/qemu/qemu/commit/a2f04333a340282c0842e76c055297cb7ba56f0f
  Author: Michael Matz <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/gdbstub.c

  Log Message:
  -----------
  ppc: Fix size of ppc64 xer register

The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's).  But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)

That mismatch leads to the following message when attaching
with gdb:

  Truncated register 32 in remote 'g' packet

(and following on that qemu stops responding).  The simple fix is
to say the truth in the .xml file.  But the better fix is to
actually make it 32bit on the wire, as old gdbs don't support
XML files for describing registers.  Also the XER state in qemu
doesn't seem to use the high 32 bits, so sending it off to gdb
doesn't seem worthwhile.

Signed-off-by: Michael Matz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 99d45f8fbd6756c2495bcb554dcbf50585f1f7b0
      
https://github.com/qemu/qemu/commit/99d45f8fbd6756c2495bcb554dcbf50585f1f7b0
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Fix reserved bit mask of dstst instruction

According to the Vector/SIMD extension documentation bit 6 that is
currently masked is valid (listed as transient bit) but bits 7 and 8
should be reserved instead. Fix the mask to match this.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8a4fd427fe8236bb4f6993702112f058b5d80507
      
https://github.com/qemu/qemu/commit/8a4fd427fe8236bb4f6993702112f058b5d80507
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/compat.h

  Log Message:
  -----------
  spapr: Introduce pseries-2.13 machine type

Signed-off-by: David Gibson <address@hidden>


  Commit: 0de6e2a3ca2e1215a2d62d8d796589d27eca91d0
      
https://github.com/qemu/qemu/commit/0de6e2a3ca2e1215a2d62d8d796589d27eca91d0
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M exec.c
    M target/ppc/kvm.c
    M util/mmap-alloc.c

  Log Message:
  -----------
  Make qemu_mempath_getpagesize() accept NULL

qemu_mempath_getpagesize() gets the effective (host side) page size for
a block of memory backed by an mmap()ed file on the host.  It requires
the mem_path parameter to be non-NULL.

This ends up meaning all the callers need a different case for handling
anonymous memory (for memory-backend-ram or default memory with -mem-path
is not specified).

We can make all those callers a little simpler by having
qemu_mempath_getpagesize() accept NULL, and treat that as the anonymous
memory case.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>


  Commit: 2b10808539d7ace3d9b1226a71a68e2431ef2176
      
https://github.com/qemu/qemu/commit/2b10808539d7ace3d9b1226a71a68e2431ef2176
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M backends/hostmem.c
    M exec.c
    M include/sysemu/hostmem.h
    M target/ppc/kvm.c

  Log Message:
  -----------
  Add host_memory_backend_pagesize() helper

There are a couple places (one generic, one target specific) where we need
to get the host page size associated with a particular memory backend.  I
have some upcoming code which will add another place which wants this.  So,
for convenience, add a helper function to calculate this.

host_memory_backend_pagesize() returns the host pagesize for a given
HostMemoryBackend object.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>


  Commit: 1d36c75a9ebf6bddbdb46693052a48ef134f3699
      
https://github.com/qemu/qemu/commit/1d36c75a9ebf6bddbdb46693052a48ef134f3699
  Author: Greg Kurz <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: drop useless sanity check in spapr_irq_alloc*()

Both spapr_irq_alloc() and spapr_irq_alloc_block() have an errp
parameter, but they don't use it if XICS hasn't been initialized
yet.

This is doubly wrong:

- all callers do pass a non-null Error **, ie, they expect an error
  to be propagated in case of failure

- XICS obviously needs to be initialized before anything starts allocating
  IRQs

So this patch turns the check into an assert.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e47f1d2786c3d01a7894a493aafe0efa6b64453c
      
https://github.com/qemu/qemu/commit/e47f1d2786c3d01a7894a493aafe0efa6b64453c
  Author: Serhii Popovych <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  Revert "spapr: Don't allow memory hotplug to memory less nodes"

This reverts commit b556854bd8524c26b8be98ab1bfdf0826831e793.

Leave change @node type from uint32_t to to int from reverted commit
because node < 0 is always false.

Note that implementing capability or some trick to detect if guest
kernel does not support hot-add to memory: this returns previous
behavour where memory added to first non-empty node.

Signed-off-by: Serhii Popovych <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b2692d5fed8b0549d70426d75c9ad4734dc557c8
      
https://github.com/qemu/qemu/commit/b2692d5fed8b0549d70426d75c9ad4734dc557c8
  Author: Greg Kurz <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: drop useless dynamic sysbus device sanity check

Since commit 7da79a167aa11, the machine class init function registers
dynamic sysbus device types it supports. Passing an unsupported device
type on the command line causes QEMU to exit with an error message
just after machine init.

It is hence not needed to do the same sanity check at machine reset.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e850da556d69363e6846ab00ddcbf7cb55203981
      
https://github.com/qemu/qemu/commit/e850da556d69363e6846ab00ddcbf7cb55203981
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Standardize instance_init and realize function names

Because of the various hooks called some variant on "init" - and the rather
greater number that used to exist, I'm always wondering when a function
called simply "*_init" or "*_initfn" will be called.

To make it easier on myself, and maybe others, rename the instance_init
hooks for ppc cpus to *_instance_init().  While we're at it rename the
realize time hooks to *_realize() (from *_realizefn()) which seems to be
the more common current convention.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 197600ecc4f81b9be5e233d8a1cbf42a48cdd371
      
https://github.com/qemu/qemu/commit/197600ecc4f81b9be5e233d8a1cbf42a48cdd371
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Simplify cpu valid check in ppc_cpu_realize

The #if isn't necessary, because there's a suitable one inside
ppc_cpu_is_valid().  We've already filtered for suitable cpu models in the
functions that search and register them.  So by the time we get to realize
having an invalid one indicates a code error, not a user error, so an
assert() is more appropriate than error_setg().

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 644a2c99a90b95957fd56fc3b9f8908ac9e90702
      
https://github.com/qemu/qemu/commit/644a2c99a90b95957fd56fc3b9f8908ac9e90702
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/fdt.c
    M hw/ppc/pnv.c
    M hw/ppc/spapr.c
    M include/hw/ppc/fdt.h

  Log Message:
  -----------
  target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()

As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
change will make some things simpler later on.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>


  Commit: 8fe08fac1939815950b74fb7eb17101320450ca7
      
https://github.com/qemu/qemu/commit/8fe08fac1939815950b74fb7eb17101320450ca7
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Avoid taking "env" parameter to mmu-hash64 functions

In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
CPUPPCState.

For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.

In theory this makes more work for the functions, but since "cs", "cpu"
and "env" are related by at most constant offsets, the compiler should be
able to optimize out the difference at effectively zero cost.

helper_*() functions are left alone - since they're more closely tied to
the TCG generated code, passing "env" is still the standard there.

While we're there, fix an incorrect indentation.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>


  Commit: dc71b55956b45a4aa6f280b57a3088d169bfc636
      
https://github.com/qemu/qemu/commit/dc71b55956b45a4aa6f280b57a3088d169bfc636
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/cpu-qom.h
    M target/ppc/kvm.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Remove fallback 64k pagesize information

CPU definitions for cpus with the 64-bit hash MMU can include a table of
available pagesizes.  If this isn't supplied ppc_cpu_instance_init() will
fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.

However, it turns out all the cpus which support 64K pages already include
an explicit table of page sizes, so there's no point to the fallback table
including 64k pages.

That removes the only place which tests POWERPC_MMU_64K, so we can remove
it.  Which in turn allows some logic to be removed from
kvm_fixup_page_sizes().

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: a059471d2536dad316dfc24dd03790d0cd597081
      
https://github.com/qemu/qemu/commit/a059471d2536dad316dfc24dd03790d0cd597081
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Move page size setup to helper function

Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.

We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: b07c59f7c8df6efc24576f07622b61ad115468e6
      
https://github.com/qemu/qemu/commit/b07c59f7c8df6efc24576f07622b61ad115468e6
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/fdt.c
    M target/ppc/cpu-qom.h
    M target/ppc/cpu.h
    M target/ppc/kvm.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Split page size information into a separate allocation

env->sps contains page size encoding information as an embedded structure.
Since this information is specific to 64-bit hash MMUs, split it out into
a separately allocated structure, to reduce the basic env size for other
cpus.  Along the way we make a few other cleanups:

    * Rename to PPCHash64Options which is more in line with qemu name
      conventions, and reflects that we're going to merge some more hash64
      mmu specific details in there in future.  Also rename its
      substructures to match qemu conventions.

    * Move structure definitions to the mmu-hash64.[ch] files.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>


  Commit: 21e405f1ecd16a9036d838222f2212ec10370059
      
https://github.com/qemu/qemu/commit/21e405f1ecd16a9036d838222f2212ec10370059
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs

Currently some cpus set the hash64_opts field in the class structure, with
specific details of their variant of the 64-bit hash mmu.  For the
remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.

But there are only a couple of cpus that use those fallbacks, so just have
them to set the has64_opts field instead, simplifying the logic.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 58969eeece99abd6d31d530ad371e789419ec9bf
      
https://github.com/qemu/qemu/commit/58969eeece99abd6d31d530ad371e789419ec9bf
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/spapr.c
    M target/ppc/cpu-qom.h
    M target/ppc/kvm.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h

  Log Message:
  -----------
  target/ppc: Move 1T segment and AMR options to PPCHash64Options

Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well.  This makes which bits of the
field should be compared pretty confusing.

Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
hash MMU into a new flags field in PPCHash64Options structure.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 26cd35b8613881c410d5226e6dc56e7bfb4b83d1
      
https://github.com/qemu/qemu/commit/26cd35b8613881c410d5226e6dc56e7bfb4b83d1
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M target/ppc/cpu.h
    M target/ppc/kvm.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Fold ci_large_pages flag into PPCHash64Options

The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory).  Fold it as another
flag into the PPCHash64Options structure.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: ca79b3b7fd0757ceb6436d4407e26c8b511a4080
      
https://github.com/qemu/qemu/commit/ca79b3b7fd0757ceb6436d4407e26c8b511a4080
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/cpu-qom.h
    M target/ppc/mmu-hash64.c

  Log Message:
  -----------
  target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model

The only place we test this flag is in conjunction with
ppc64_use_proc_tbl().  That checks for the LPCR_UPRT bit, which we already
ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 0941d728a4636f68523d99a729e24ee12c36d440
      
https://github.com/qemu/qemu/commit/0941d728a4636f68523d99a729e24ee12c36d440
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/cpu-qom.h
    M target/ppc/kvm.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Get rid of POWERPC_MMU_VER() macros

These macros were introduced to deal with the fact that the mmu_model
field has bit flags mixed in with what's otherwise an enum of various mmu
types.

We've now eliminated all those flags except for one, and that one -
POWERPC_MMU_64 - is already included/compared in the MMU_VER macros.  So,
we can get rid of those macros and just directly compare mmu_model values
in the places it was used.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 67d7d66f27c49a87c6f28ccff814f5d7eaaccec6
      
https://github.com/qemu/qemu/commit/67d7d66f27c49a87c6f28ccff814f5d7eaaccec6
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/spapr.c
    M target/ppc/cpu.h
    M target/ppc/kvm.c
    M target/ppc/machine.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Fold slb_nr into PPCHash64Options

The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer).
This is another static-after-initialization parameter of the specific
version of the 64-bit hash MMU in the CPU.  So, this patch folds the field
into PPCHash64Options with the other hash MMU options.

This is a bit more complicated that the things previously put in there,
because slb_nr was foolishly included in the migration stream.  So we need
some of the usual dance to handle backwards compatible migration.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: da9f80fbad21319194e73355dea8a1cff6a574e4
      
https://github.com/qemu/qemu/commit/da9f80fbad21319194e73355dea8a1cff6a574e4
  Author: Serhii Popovych <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Add ibm,max-associativity-domains property

Now recent kernels (i.e. since linux-stable commit a346137e9142
("powerpc/numa: Use ibm,max-associativity-domains to discover possible nodes")
support this property to mark initially memory-less NUMA nodes as "possible"
to allow further memory hot-add to them.

Advertise this property for pSeries machines to let guest kernels detect
maximum supported node configuration and benefit from kernel side change
when hot-add memory to specific, possibly empty before, NUMA node.

Signed-off-by: Serhii Popovych <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 03f048090ee73bfb18b16a5dc462b5411120fb4d
      
https://github.com/qemu/qemu/commit/03f048090ee73bfb18b16a5dc462b5411120fb4d
  Author: Igor Mammedov <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/e500plat.c
    M hw/ppc/mpc8544ds.c

  Log Message:
  -----------
  ppc: e500: switch E500 based machines to full machine definition

Convert PPCE500Params to PCCE500MachineClass which it essentially is,
and introduce PCCE500MachineState to keep track of E500 specific
state instead of adding global variables or extra parameters to
functions when we need to keep data beyond machine init
(i.e. make it look like typical fully defined machine).

It's pretty shallow conversion instead of currently used trivial
DEFINE_MACHINE() macro. It adds extra 60LOC of boilerplate code
of full machine definition.

The patch on top[1] will use PCCE500MachineState to keep track of
platform_bus device and add E500Plate specific machine class
to use HOTPLUG_HANDLER for explicitly initializing dynamic
sysbus devices at the time they are added instead of delaying
it to machine done time by platform_bus_init_notify() which is
being removed.

1)  <address@hidden>

Signed-off-by: Igor Mammedov <address@hidden>
Suggested-by: David Gibson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a324d6f166970f8f6a82c61ffd2356fbda81c8f4
      
https://github.com/qemu/qemu/commit/a324d6f166970f8f6a82c61ffd2356fbda81c8f4
  Author: Bharata B Rao <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M docs/specs/ppc-spapr-hotplug.txt
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr_ovec.h

  Log Message:
  -----------
  spapr: Support ibm,dynamic-memory-v2 property

The new property ibm,dynamic-memory-v2 allows memory to be represented
in a more compact manner in device tree.

Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4550f6a5da691fa45e801f391e947ff4236d1fa6
      
https://github.com/qemu/qemu/commit/4550f6a5da691fa45e801f391e947ff4236d1fa6
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()

cpu_ppc_set_papr() removes the EP and HV bits from the MSR mask.  While
removing the HV bit makes sense (a cpu in PAPR mode should never be
emulated in hypervisor mode), the EP bit is just bizarre.  Although it's
true that a papr mode guest shouldn't be able to change the exception
prefix, the MSR[EP] bit doesn't even exist on the cpus supported for PAPR
mode, so it's pointless to do anything with it here.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>


  Commit: 88f42c6773c0c09f5c38d5eb0cd6e8b7aed4dfeb
      
https://github.com/qemu/qemu/commit/88f42c6773c0c09f5c38d5eb0cd6e8b7aed4dfeb
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: Set compatibility mode before the rest of spapr_cpu_reset()

Although the order doesn't really matter at the moment, it's possible
other initializastions could depend on the compatiblity mode, so make sure
we set it first in spapr_cpu_reset().

While we're at it drop the test against first_cpu.  Setting the compat mode
to the value it already has is redundant, but harmless, so we might as well
make a small simplification to the code.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>


  Commit: 6233b679cae8741890f981c9dd6570d47715141e
      
https://github.com/qemu/qemu/commit/6233b679cae8741890f981c9dd6570d47715141e
  Author: David Gibson <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M numa.c

  Log Message:
  -----------
  Clear mem_path if we fall back to anonymous RAM allocation

If the -mem-path option is set, we attempt to map the guest's RAM from a
file in the given path; it's usually used to back guest RAM with hugepages.
If we're unable to (e.g. not enough free hugepages) then we fall back to
allocating normal anonymous pages.  This behaviour can be surprising, but a
comment in allocate_system_memory_nonnuma() suggests it's legacy behaviour
we can't change.

What really isn't ok, though, is that in this case we leave mem_path set.
That means functions which attempt to determine the pagesize of main RAM
can erroneously think it is hugepage based on the requested path, even
though it's not.

This is particular bad for the pseries machine type.  KVM HV limitations
mean the guest can't use pagesizes larger than the host page size used to
back RAM.  That means that such a fallback, rather than merely giving
poorer performance than expected will cause the guest to freeze up early in
boot as it attempts to use large page mappings that can't work.

This patch addresses the problem by clearing the mem_path variable when we
fall back to anonymous pages, meaning that subsequent attempts to
determine the RAM page size will get an accurate result.

Signed-off-by: David Gibson <address@hidden>


  Commit: dcbd26f881557b83b99869b138b337feaf2d705d
      
https://github.com/qemu/qemu/commit/dcbd26f881557b83b99869b138b337feaf2d705d
  Author: Peter Maydell <address@hidden>
  Date:   2018-04-27 (Fri, 27 Apr 2018)

  Changed paths:
    M backends/hostmem.c
    M docs/specs/ppc-spapr-hotplug.txt
    M exec.c
    M hw/intc/heathrow_pic.c
    M hw/misc/macio/macio.c
    M hw/pci-host/grackle.c
    M hw/pci-host/uninorth.c
    M hw/ppc/e500.c
    M hw/ppc/e500.h
    M hw/ppc/e500plat.c
    M hw/ppc/fdt.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/mpc8544ds.c
    M hw/ppc/pnv.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/compat.h
    M include/hw/intc/heathrow_pic.h
    M include/hw/misc/macio/macio.h
    A include/hw/pci-host/uninorth.h
    M include/hw/ppc/fdt.h
    M include/hw/ppc/spapr_ovec.h
    M include/sysemu/hostmem.h
    M numa.c
    M target/ppc/cpu-qom.h
    M target/ppc/cpu.h
    M target/ppc/gdbstub.c
    M target/ppc/kvm.c
    M target/ppc/machine.c
    M target/ppc/mmu-hash64.c
    M target/ppc/mmu-hash64.h
    M target/ppc/mmu_helper.c
    M target/ppc/translate.c
    M target/ppc/translate_init.c
    M util/mmap-alloc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180427' 
into staging

ppc patch queue 2018-04-27

Here's the first batch of ppc patches for 2.13.  This has a lot of
stuff that's accumulated during the 2.12 freeze.  Highlights are:

    * Many improvements for the Uninorth PCI host bridge for Mac
      machine types
    * Preliminary helpers improve handling of multiple backing
      pagesizes (not strictly ppc related, but have acks and aimed to
      allow future ppc changes)
    * Cleanups to pseries cpu initialization
    * Cleanups to hash64 MMU handling
    * Assorted bugfixes and improvements

# gpg: Signature made Fri 27 Apr 2018 10:20:30 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.13-20180427: (49 commits)
  Clear mem_path if we fall back to anonymous RAM allocation
  spapr: Set compatibility mode before the rest of spapr_cpu_reset()
  target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
  spapr: Support ibm,dynamic-memory-v2 property
  ppc: e500: switch E500 based machines to full machine definition
  spapr: Add ibm,max-associativity-domains property
  target/ppc: Fold slb_nr into PPCHash64Options
  target/ppc: Get rid of POWERPC_MMU_VER() macros
  target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
  target/ppc: Fold ci_large_pages flag into PPCHash64Options
  target/ppc: Move 1T segment and AMR options to PPCHash64Options
  target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
  target/ppc: Split page size information into a separate allocation
  target/ppc: Move page size setup to helper function
  target/ppc: Remove fallback 64k pagesize information
  target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
  target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
  target/ppc: Simplify cpu valid check in ppc_cpu_realize
  target/ppc: Standardize instance_init and realize function names
  spapr: drop useless dynamic sysbus device sanity check
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ca92651697bd...dcbd26f88155
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