[Qemu-commits] [qemu/qemu] bb8136: riscv/sifive_u: fix a memory leak in soc_realize()

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: bb8136df698bd565ee4f6c18d26c50dee320bfe4
      
https://github.com/qemu/qemu/commit/bb8136df698bd565ee4f6c18d26c50dee320bfe4
  Author: Pan Nengyuan <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv/sifive_u: fix a memory leak in soc_realize()

Fix a minor memory leak in riscv_sifive_u_soc_realize()

Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a37f21c27d3e2342c2080aafd4cfe7e949612428
      
https://github.com/qemu/qemu/commit/a37f21c27d3e2342c2080aafd4cfe7e949612428
  Author: Yiting Wang <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  riscv: Set xPIE to 1 after xRET

When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.

Signed-off-by: Yiting Wang <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 613fa160e19abe8e1fe44423fcfa8ec73d3d48e5
      
https://github.com/qemu/qemu/commit/613fa160e19abe8e1fe44423fcfa8ec73d3d48e5
  Author: ShihPo Hung <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Fix tb->flags FS status

It was found that running libquantum on riscv-linux qemu produced an
incorrect result. After investigation, FP registers are not saved
during context switch due to incorrect mstatus.FS.

In current implementation tb->flags merges all non-disabled state to
dirty. This means the code in mark_fs_dirty in translate.c that
handles initial and clean states is unreachable.

This patch fixes it and is successfully tested with:
  libquantum

Thanks to Richard for pointing out the actual bug.

v3: remove the redundant condition
v2: root cause FS problem

Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: ShihPo Hung <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a59796eb6d59bbd74ce28ddbddb1b83e60674e96
      
https://github.com/qemu/qemu/commit/a59796eb6d59bbd74ce28ddbddb1b83e60674e96
  Author: ShihPo Hung <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvd.inc.c
    M target/riscv/insn_trans/trans_rvf.inc.c

  Log Message:
  -----------
  target/riscv: fsd/fsw doesn't dirty FP state

Signed-off-by: ShihPo Hung <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 82f014671cf057de51c4a577c9e2ad637dcec6f9
      
https://github.com/qemu/qemu/commit/82f014671cf057de51c4a577c9e2ad637dcec6f9
  Author: ShihPo Hung <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M target/riscv/csr.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: update mstatus.SD when FS is set dirty

remove the check becuase SD bit should summarize FS and XS fields
unconditionally.

Signed-off-by: ShihPo Hung <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ba2ed84fe6a78f64b2da441750fc6e925d94106a
      
https://github.com/qemu/qemu/commit/ba2ed84fe6a78f64b2da441750fc6e925d94106a
  Author: Peter Maydell <address@hidden>
  Date:   2020-01-24 (Fri, 24 Jan 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_rvd.inc.c
    M target/riscv/insn_trans/trans_rvf.inc.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' 
into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 1

This patch set contains a handful of collected fixes that I'd like to target
for the 5.0 soft freeze (I know that's a long way away, I just don't know what
else to call these):

* A fix for a memory leak initializing the sifive_u board.
* Fixes to privilege mode emulation related to interrupts and fstatus.

Notably absent is the H extension implementation.  That's pretty much reviewed,
but not quite ready to go yet and I didn't want to hold back these important
fixes.  This boots 32-bit and 64-bit Linux (buildroot this time, just for fun)
and passes "make check".

# gpg: Signature made Tue 21 Jan 2020 22:55:28 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf1:
  target/riscv: update mstatus.SD when FS is set dirty
  target/riscv: fsd/fsw doesn't dirty FP state
  target/riscv: Fix tb->flags FS status
  riscv: Set xPIE to 1 after xRET
  riscv/sifive_u: fix a memory leak in soc_realize()

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a43efa34c7d7...ba2ed84fe6a7