[Qemu-commits] [qemu/qemu] 028616: target/riscv: Convert MIP CSR to target_ulong

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 028616130d5f0abc8a3b96f28963da51a875024b
      
https://github.com/qemu/qemu/commit/028616130d5f0abc8a3b96f28963da51a875024b
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Convert MIP CSR to target_ulong

The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: af1fa0039c799a350bcde07b3d8a71dfde07d11b
      
https://github.com/qemu/qemu/commit/af1fa0039c799a350bcde07b3d8a71dfde07d11b
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add the Hypervisor extension

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: bd023ce33b85d73791b7bc78fd04a8115c60995e
      
https://github.com/qemu/qemu/commit/bd023ce33b85d73791b7bc78fd04a8115c60995e
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: Add the Hypervisor CSRs to CPUState

Add the Hypervisor CSRs to CPUState and at the same time (to avoid
bisect issues) update the CSR macros for the v0.5 Hyp spec.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ab67a1d07a4f6f1b4d577c5c47013273b9804551
      
https://github.com/qemu/qemu/commit/ab67a1d07a4f6f1b4d577c5c47013273b9804551
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add support for the new execption numbers

The v0.5 Hypervisor spec add new execption numbers, let's add support
for those.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 205377f8940898e4c53d1b44350a3d4934a2da72
      
https://github.com/qemu/qemu/commit/205377f8940898e4c53d1b44350a3d4934a2da72
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Rename the H irqs to VS irqs

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ef6bb7b62682badefdcb744831510aaa5971684f
      
https://github.com/qemu/qemu/commit/ef6bb7b62682badefdcb744831510aaa5971684f
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add the virtulisation mode

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c7b1bbc80fc2af17395d3986c346fd2307e57829
      
https://github.com/qemu/qemu/commit/c7b1bbc80fc2af17395d3986c346fd2307e57829
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add the force HS exception mode

Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit
specifies if an exeption should be taken to HS mode no matter the
current delegation status. This is used when an exeption must be taken
to HS mode, such as when handling interrupts.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0a42f4c4408824dc7cb9ff60c9bdce6dcc0d24a5
      
https://github.com/qemu/qemu/commit/0a42f4c4408824dc7cb9ff60c9bdce6dcc0d24a5
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix CSR perm checking for HS mode

Update the CSR permission checking to work correctly when we are in
HS-mode.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 35f690391bd69922a1987d44546b884adaf29a57
      
https://github.com/qemu/qemu/commit/35f690391bd69922a1987d44546b884adaf29a57
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Print priv and virt in disas log

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: df30e652d42f9528e538d0a8de44879643a7fc0a
      
https://github.com/qemu/qemu/commit/df30e652d42f9528e538d0a8de44879643a7fc0a
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Dump Hypervisor registers if enabled

Dump the Hypervisor registers and the current Hypervisor state.

While we are editing this code let's also dump stvec and scause.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Atish Patra <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ff2cc1294cd8179d87de299b8e7a16bdb1e69523
      
https://github.com/qemu/qemu/commit/ff2cc1294cd8179d87de299b8e7a16bdb1e69523
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add Hypervisor CSR access functions

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 8747c9eeb2aaec8441d0900b198725ab33af4951
      
https://github.com/qemu/qemu/commit/8747c9eeb2aaec8441d0900b198725ab33af4951
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add Hypervisor virtual CSRs accesses

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 34cfb5f61842d495c6f6fc3eeb4197b5b44fd570
      
https://github.com/qemu/qemu/commit/34cfb5f61842d495c6f6fc3eeb4197b5b44fd570
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add Hypervisor machine CSRs accesses

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 66e594f2800ddc55f908830bf9e8dc4cda1304fe
      
https://github.com/qemu/qemu/commit/66e594f2800ddc55f908830bf9e8dc4cda1304fe
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add virtual register swapping function

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 713d8363deb3774db14fb88a9fcd99687dcef114
      
https://github.com/qemu/qemu/commit/713d8363deb3774db14fb88a9fcd99687dcef114
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Set VS bits in mideleg for Hyp extension

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d0e53ce33ec8f66ffa597c634d50be73264aeadb
      
https://github.com/qemu/qemu/commit/d0e53ce33ec8f66ffa597c634d50be73264aeadb
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Extend the MIE CSR to support virtulisation

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a2e9f57d06279220b1834eca2494e52adae121b8
      
https://github.com/qemu/qemu/commit/a2e9f57d06279220b1834eca2494e52adae121b8
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Extend the SIP CSR to support virtulisation

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 3ef10a098b0d3ebb02bf8e1325adc3b77af92f0b
      
https://github.com/qemu/qemu/commit/3ef10a098b0d3ebb02bf8e1325adc3b77af92f0b
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add support for virtual interrupt setting

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: eccc5a12c2fd1c646c69a1e7de29183b7a559973
      
https://github.com/qemu/qemu/commit/eccc5a12c2fd1c646c69a1e7de29183b7a559973
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/ricsv: Flush the TLB on virtulisation mode changes

To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9d0d11269671646be7475cc01142e9d3ed8ae59c
      
https://github.com/qemu/qemu/commit/9d0d11269671646be7475cc01142e9d3ed8ae59c
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Generate illegal instruction on WFI when V=1

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5eb9e782f523d2898e2dacd86c6e41365dae74b3
      
https://github.com/qemu/qemu/commit/5eb9e782f523d2898e2dacd86c6e41365dae74b3
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Add hypvervisor trap support

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e3fba4bab668a41f7cec6405c5aeb21497bd7c83
      
https://github.com/qemu/qemu/commit/e3fba4bab668a41f7cec6405c5aeb21497bd7c83
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Add Hypervisor trap return support

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a
      
https://github.com/qemu/qemu/commit/895c412cb6e79b7b08bd3c2d2fcb70a3cab6ff8a
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c

  Log Message:
  -----------
  target/riscv: Add hfence instructions

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0736febb2d0e1bb503ca07091c16a16e78480366
      
https://github.com/qemu/qemu/commit/0736febb2d0e1bb503ca07091c16a16e78480366
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c

  Log Message:
  -----------
  target/riscv: Remove the hret instruction

The hret instruction does not exist in the new spec versions, so remove
it from QEMU.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e28eaed87902c5e852c3ed043b27204e879aa4e2
      
https://github.com/qemu/qemu/commit/e28eaed87902c5e852c3ed043b27204e879aa4e2
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Only set TB flags with FP status if enabled

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 29409c1d921d607873268671bf11a088efb5558e
      
https://github.com/qemu/qemu/commit/29409c1d921d607873268671bf11a088efb5558e
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Disable guest FP support based on virtual status

When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 45b4dc8b403aa5473ec015336adf7d14d88e85c5
      
https://github.com/qemu/qemu/commit/45b4dc8b403aa5473ec015336adf7d14d88e85c5
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Mark both sstatus and msstatus_hs as dirty

Mark both sstatus and vsstatus as dirty (3).

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ae84dd0ab7eaf7e98cd6ee05b2063cce8ff9bc02
      
https://github.com/qemu/qemu/commit/ae84dd0ab7eaf7e98cd6ee05b2063cce8ff9bc02
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Respect MPRV and SPRV for floating point ops

mark_fs_dirty() is the only place in translate.c that uses the
virt_enabled bool. Let's respect the contents of MSTATUS.MPRV and
HSTATUS.SPRV when setting the bool as this is used for performing
floating point operations when V=0.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1448689c7b23690f49a4cce248c6e4ac973d37b8
      
https://github.com/qemu/qemu/commit/1448689c7b23690f49a4cce248c6e4ac973d37b8
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Allow specifying MMU stage

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 36a18664bafcfafa5e997b47458387f6fe53d537
      
https://github.com/qemu/qemu/commit/36a18664bafcfafa5e997b47458387f6fe53d537
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Implement second stage MMU

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b2ef6ab9fee6948cf016f9e741feecdfb333fcbe
      
https://github.com/qemu/qemu/commit/b2ef6ab9fee6948cf016f9e741feecdfb333fcbe
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Raise the new execptions when 2nd stage translation fails

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 3067553993ae986b76a92df8a978778134ecdc84
      
https://github.com/qemu/qemu/commit/3067553993ae986b76a92df8a978778134ecdc84
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Set htval and mtval2 on execptions

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 551fa7e8a695ea5fd1cca8ffd318556855bbf54f
      
https://github.com/qemu/qemu/commit/551fa7e8a695ea5fd1cca8ffd318556855bbf54f
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Add support for the 32-bit MSTATUSH CSR

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e44b50b5b2e508fdd24915ab0e44ac49685e1de3
      
https://github.com/qemu/qemu/commit/e44b50b5b2e508fdd24915ab0e44ac49685e1de3
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add the MSTATUS_MPV_ISSET helper macro

Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c9eefe05a42d05d7a6dc49805f123579e5558d5d
      
https://github.com/qemu/qemu/commit/c9eefe05a42d05d7a6dc49805f123579e5558d5d
  Author: Alistair Francis <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Allow enabling the Hypervisor extension

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: acead54c78c7294612f529413673eb4286fb8b18
      
https://github.com/qemu/qemu/commit/acead54c78c7294612f529413673eb4286fb8b18
  Author: Bin Meng <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: virt: Allow PCI address 0

When testing e1000 with the virt machine, e1000's I/O space cannot
be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
written with address 0 plus I/O enable bit, but QEMU's "info pci"
shows that:

  Bus  0, device   1, function 0:
    Ethernet controller: PCI device 8086:100e
  ...
      BAR1: I/O at 0xffffffffffffffff [0x003e].
  ...

It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c695724868ce4049fd79c5a509880dbdf171e744
      
https://github.com/qemu/qemu/commit/c695724868ce4049fd79c5a509880dbdf171e744
  Author: Anup Patel <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Emulate TIME CSRs for privileged mode

Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.

For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.

We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5f3616ccceb5d5c49f99838c78498e581fb42fc5
      
https://github.com/qemu/qemu/commit/5f3616ccceb5d5c49f99838c78498e581fb42fc5
  Author: Anup Patel <address@hidden>
  Date:   2020-02-27 (Thu, 27 Feb 2020)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_clint.h

  Log Message:
  -----------
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation

This patch extends CLINT emulation to provide rdtime callback for
TCG. This rdtime callback will be called wheneven TIME CSRs are
read in privileged modes.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 2ac031d171ccd18c973014d9978b4a63f0ad5fb0
      
https://github.com/qemu/qemu/commit/2ac031d171ccd18c973014d9978b4a63f0ad5fb0
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-03 (Tue, 03 Mar 2020)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_clint.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' 
into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 3

This pull request is almost entirely an implementation of the draft hypervisor
extension.  This extension is still in draft and is expected to have
incompatible changes before being frozen, but we've had good luck managing
other RISC-V draft extensions in QEMU so far.

Additionally, there's a fix to PCI addressing and some improvements to the
M-mode timer.

This boots linux and passes make check for me.

# gpg: Signature made Tue 03 Mar 2020 00:23:20 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf3: (38 commits)
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation
  target/riscv: Emulate TIME CSRs for privileged mode
  riscv: virt: Allow PCI address 0
  target/riscv: Allow enabling the Hypervisor extension
  target/riscv: Add the MSTATUS_MPV_ISSET helper macro
  target/riscv: Add support for the 32-bit MSTATUSH CSR
  target/riscv: Set htval and mtval2 on execptions
  target/riscv: Raise the new execptions when 2nd stage translation fails
  target/riscv: Implement second stage MMU
  target/riscv: Allow specifying MMU stage
  target/riscv: Respect MPRV and SPRV for floating point ops
  target/riscv: Mark both sstatus and msstatus_hs as dirty
  target/riscv: Disable guest FP support based on virtual status
  target/riscv: Only set TB flags with FP status if enabled
  target/riscv: Remove the hret instruction
  target/riscv: Add hfence instructions
  target/riscv: Add Hypervisor trap return support
  target/riscv: Add hypvervisor trap support
  target/riscv: Generate illegal instruction on WFI when V=1
  target/ricsv: Flush the TLB on virtulisation mode changes
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c81acb643a61...2ac031d171cc