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[Qemu-commits] [qemu/qemu] 9bb6d1: aspeed: Add boot stub for smp booting
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 9bb6d1: aspeed: Add boot stub for smp booting |
Date: |
Mon, 11 May 2020 08:45:34 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9bb6d14081ce0859480168b1c322b6a88706161e
https://github.com/qemu/qemu/commit/9bb6d14081ce0859480168b1c322b6a88706161e
Author: Joel Stanley <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Add boot stub for smp booting
This is a boot stub that is similar to the code u-boot runs, allowing
the kernel to boot the secondary CPU.
u-boot works as follows:
1. Initialises the SMP mailbox area in the SCU at 0x1e6e2180 with default
values
2. Copies a stub named 'mailbox_insn' from flash to the SCU, just above the
mailbox area
3. Sets AST_SMP_MBOX_FIELD_READY to a magic value to indicate the
secondary can begin execution from the stub
4. The stub waits until the AST_SMP_MBOX_FIELD_GOSIGN register is set to
a magic value
5. Jumps to the address in AST_SMP_MBOX_FIELD_ENTRY, starting Linux
Linux indicates it is ready by writing the address of its entrypoint
function to AST_SMP_MBOX_FIELD_ENTRY and the 'go' magic number to
AST_SMP_MBOX_FIELD_GOSIGN. The secondary CPU sees this at step 4 and
breaks out of it's loop.
To be compatible, a fixed qemu stub is loaded into the mailbox area. As
qemu can ensure the stub is loaded before execution starts, we do not
need to emulate the AST_SMP_MBOX_FIELD_READY behaviour of u-boot. The
secondary CPU's program counter points to the beginning of the stub,
allowing qemu to start secondaries at step four.
Reboot behaviour is preserved by resetting AST_SMP_MBOX_FIELD_GOSIGN
when the secondaries are reset.
This is only configured when the system is booted with -kernel and qemu
does not execute u-boot first.
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 93dd1e6140e2652347cfe7208591d4cd32762d08
https://github.com/qemu/qemu/commit/93dd1e6140e2652347cfe7208591d4cd32762d08
Author: Edgar E. Iglesias <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Drop access_el3_aa32ns_aa64any()
Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.
Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7582591ae745f224a58fd9a36e3b9230fb03bfc2
https://github.com/qemu/qemu/commit/7582591ae745f224a58fd9a36e3b9230fb03bfc2
Author: Joel Stanley <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2600.c
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
aspeed: Support AST2600A1 silicon revision
There are minimal differences from Qemu's point of view between the A0
and A1 silicon revisions.
As the A1 exercises different code paths in u-boot it is desirable to
emulate that instead.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f4ab4f8e772700dcef1c99b75b0704bd5ca96b6a
https://github.com/qemu/qemu/commit/f4ab4f8e772700dcef1c99b75b0704bd5ca96b6a
Author: Joel Stanley <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/misc/aspeed_sdmc.c
Log Message:
-----------
aspeed: sdmc: Implement AST2600 locking behaviour
The AST2600 handles this differently with the extra 'hardlock' state, so
move the testing to the soc specific class' write callback.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 54595a5731ed7c94491008b0d3835ad3f786dbcc
https://github.com/qemu/qemu/commit/54595a5731ed7c94491008b0d3835ad3f786dbcc
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/arm/nrf51_soc.c
M hw/i2c/microbit_i2c.c
M hw/timer/nrf51_timer.c
M include/hw/arm/nrf51.h
M include/hw/i2c/microbit_i2c.h
Log Message:
-----------
hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition
On the NRF51 series, all peripherals have a fixed I/O size
of 4KiB. Define NRF51_PERIPHERAL_SIZE and use it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 27d6dea3d702b4f9cefacfc8438a9478c03092e4
https://github.com/qemu/qemu/commit/27d6dea3d702b4f9cefacfc8438a9478c03092e4
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/arm/nrf51_soc.c
M hw/timer/nrf51_timer.c
M hw/timer/trace-events
M include/hw/timer/nrf51_timer.h
Log Message:
-----------
hw/timer/nrf51_timer: Display timer ID in trace events
The NRF51 series SoC have 3 timer peripherals, each having
4 counters. To help differentiate which peripheral is accessed,
display the timer ID in the trace events.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 602ab789363741aee29aeacc6b024af72161f3f7
https://github.com/qemu/qemu/commit/602ab789363741aee29aeacc6b024af72161f3f7
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/timer/nrf51_timer.c
M hw/timer/trace-events
Log Message:
-----------
hw/timer/nrf51_timer: Add trace event of counter value update
Add trace event to display timer's counter value updates.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 390734a42d003848efc6b73f6b7d8cd8aff8bdab
https://github.com/qemu/qemu/commit/390734a42d003848efc6b73f6b7d8cd8aff8bdab
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M include/hw/core/cpu.h
Log Message:
-----------
exec: Add block comments for watchpoint routines
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9835936d4450dccd5e6fabd3c34330420036b028
https://github.com/qemu/qemu/commit/9835936d4450dccd5e6fabd3c34330420036b028
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M exec.c
Log Message:
-----------
exec: Fix cpu_watchpoint_address_matches address length
The only caller of cpu_watchpoint_address_matches passes
TARGET_PAGE_SIZE, so the bug is not currently visible.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 857129b34190a4c2e782006dc255352a6cd3934b
https://github.com/qemu/qemu/commit/857129b34190a4c2e782006dc255352a6cd3934b
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Add block comment for probe_access
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7a1bfee682d8474340ec0fced19b9f0faef9f568
https://github.com/qemu/qemu/commit/7a1bfee682d8474340ec0fced19b9f0faef9f568
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Adjust probe_access call to page_check_range
We have validated that addr+size does not cross a page boundary.
Therefore we need to validate exactly one page. We can achieve
that passing any value 1 <= x <= size to page_check_range.
Passing 1 will simplify the next patch.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 069cfe77d63e06e2b25912aea9fea6ea14bb246a
https://github.com/qemu/qemu/commit/069cfe77d63e06e2b25912aea9fea6ea14bb246a
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/exec/cpu-all.h
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Add probe_access_flags
This new interface will allow targets to probe for a page
and then handle watchpoints themselves. This will be most
useful for vector predicated memory operations, where one
page lookup can be used for many operations, and one test
can avoid many watchpoint checks.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: b9e60257c10a0116318dc4e23148f7e4d85811a8
https://github.com/qemu/qemu/commit/b9e60257c10a0116318dc4e23148f7e4d85811a8
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M docs/devel/loads-stores.rst
M include/exec/cpu_ldst.h
Log Message:
-----------
accel/tcg: Add endian-specific cpu_{ld, st}* operations
We currently have target-endian versions of these operations,
but no easy way to force a specific endianness. This can be
helpful if the target has endian-specific operations, or a mode
that swaps endianness.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6799ce7b0e11f4b08c5cf26d08707b829f69449c
https://github.com/qemu/qemu/commit/6799ce7b0e11f4b08c5cf26d08707b829f69449c
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn
Use the "normal" memory access functions, rather than the
softmmu internal helper functions directly.
Since fb901c905dc3, cpu_mem_index is now a simple extract
from env->hflags and not a large computation. Which means
that it's now more work to pass around this value than it
is to recompute it.
This only adjusts the primitives, and does not clean up
all of the uses within sve_helper.c.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f32e2ab65f3a0fc03d58936709e5a565c4b0db50
https://github.com/qemu/qemu/commit/f32e2ab65f3a0fc03d58936709e5a565c4b0db50
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Drop manual handling of set/clear_helper_retaddr
Since we converted back to cpu_*_data_ra, we do not need to
do this ourselves.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b4cd95d2f4c7197b844f51b29871d888063ea3e7
https://github.com/qemu/qemu/commit/b4cd95d2f4c7197b844f51b29871d888063ea3e7
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Add sve infrastructure for page lookup
For contiguous predicated memory operations, we want to
minimize the number of tlb lookups performed. We have
open-coded this for sve_ld1_r, but for correctness with
MTE we will need this for all of the memory operations.
Create a structure that holds the bounds of active elements,
and metadata for two pages. Add routines to find those
active elements, lookup the pages, and run watchpoints
for those pages.
Temporarily mark the functions unused to avoid Werror.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cf4a49b71b1712142d7122025a8ca7ea5b59d73f
https://github.com/qemu/qemu/commit/cf4a49b71b1712142d7122025a8ca7ea5b59d73f
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Adjust interface of sve_ld1_host_fn
The current interface includes a loop; change it to load a
single element. We will then be able to use the function
for ld{2,3,4} where individual vector elements are not adjacent.
Replace each call with the simplest possible loop over active
elements.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b854fd06a868e0308bcfe05ad0a71210705814c7
https://github.com/qemu/qemu/commit/b854fd06a868e0308bcfe05ad0a71210705814c7
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Use SVEContLdSt in sve_ld1_r
First use of the new helper functions, so we can remove the
unused markup. No longer need a scratch for user-only, as
we completely probe the page set before reading; system mode
still requires a scratch for MMIO.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4bcc3f0ff8e5ae2b17b5aab9aa613ff1b8025896
https://github.com/qemu/qemu/commit/4bcc3f0ff8e5ae2b17b5aab9aa613ff1b8025896
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Handle watchpoints in sve_ld1_r
Handle all of the watchpoints for active elements all at once,
before we've modified the vector register. This removes the
TLB_WATCHPOINT bit from page[].flags, which means that we can
use the normal fast path via RAM.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5c9b8458a0b3008d24d84b67e1c9b6d5f39f4d66
https://github.com/qemu/qemu/commit/5c9b8458a0b3008d24d84b67e1c9b6d5f39f4d66
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Use SVEContLdSt for multi-register contiguous loads
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c647673ce4d72a8789703c62a7f3cbc732cb1ea8
https://github.com/qemu/qemu/commit/c647673ce4d72a8789703c62a7f3cbc732cb1ea8
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Update contiguous first-fault and no-fault loads
With sve_cont_ldst_pages, the differences between first-fault and no-fault
are minimal, so unify the routines. With cpu_probe_watchpoint, we are able
to make progress through pages with TLB_WATCHPOINT set when the watchpoint
does not actually fire.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0fa476c1bb37a70df7eeff1e5bfb4791feb37e0e
https://github.com/qemu/qemu/commit/0fa476c1bb37a70df7eeff1e5bfb4791feb37e0e
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Use SVEContLdSt for contiguous stores
Follow the model set up for contiguous loads. This handles
watchpoints correctly for contiguous stores, recognizing the
exception before any changes to memory.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 50de9b78cec06e6d16e92a114a505779359ca532
https://github.com/qemu/qemu/commit/50de9b78cec06e6d16e92a114a505779359ca532
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Reuse sve_probe_page for gather first-fault loads
This avoids the need for a separate set of helpers to implement
no-fault semantics, and will enable MTE in the future.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 88a660a48ef513ce9875b595e19b2a820b3f3fca
https://github.com/qemu/qemu/commit/88a660a48ef513ce9875b595e19b2a820b3f3fca
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Reuse sve_probe_page for scatter stores
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 10a85e2c8ab6e004e7f3f1dcfea8cb0bf58fb9fb
https://github.com/qemu/qemu/commit/10a85e2c8ab6e004e7f3f1dcfea8cb0bf58fb9fb
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Reuse sve_probe_page for gather loads
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: ba080b8682fc6bde7f2d9dedddb519d63cbe138f
https://github.com/qemu/qemu/commit/ba080b8682fc6bde7f2d9dedddb519d63cbe138f
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/internals.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Remove sve_memopidx
None of the sve helpers use TCGMemOpIdx any longer, so we can
stop passing it.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f5cbb280bdd2cb5b8f44db015571591ef3c42665
https://github.com/qemu/qemu/commit/f5cbb280bdd2cb5b8f44db015571591ef3c42665
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/kvm32.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm/kvm: Inline set_feature() calls
We want to move the inlined declarations of set_feature()
from cpu*.c to cpu.h. To avoid clashing with the KVM
declarations, inline the few KVM calls.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5fda95041d7237ab35733ceb66e0cb89f6107169
https://github.com/qemu/qemu/commit/5fda95041d7237ab35733ceb66e0cb89f6107169
Author: Thomas Huth <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Make set_feature() available for other files
Move the common set_feature() and unset_feature() functions
from cpu.c and cpu64.c to cpu.h.
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-ID: <address@hidden>
[PMD: Split Thomas's patch in two: set_feature, cpu_register]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 92b6a659388ab3735e5fbb17ac486923b681f57f
https://github.com/qemu/qemu/commit/92b6a659388ab3735e5fbb17ac486923b681f57f
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
Use ARRAY_SIZE() to iterate over ARMCPUInfo[].
Since on the aarch64-linux-user build, arm_cpus[] is empty, add
the cpu_count variable and only iterate when it is non-zero.
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fcdf0a90f791038c7e0a8546d00ca3168a7f3891
https://github.com/qemu/qemu/commit/fcdf0a90f791038c7e0a8546d00ca3168a7f3891
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
As IDAU is a v8M feature, restrict it to the Aarch32 CPUs.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2465b07c0bd4f7a97bbcbefbd7f7432230485bea
https://github.com/qemu/qemu/commit/2465b07c0bd4f7a97bbcbefbd7f7432230485bea
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/Makefile.objs
M target/arm/cpu.c
A target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Restrict TCG cpus to TCG accel
A KVM-only build won't be able to run TCG cpus.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4758567bc00ee52e0861202206f4b8fab5e1af90
https://github.com/qemu/qemu/commit/4758567bc00ee52e0861202206f4b8fab5e1af90
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M hw/arm/musicpal.c
Log Message:
-----------
hw/arm/musicpal: Map the UART devices unconditionally
I can't find proper documentation or datasheet, but it is likely
a MMIO mapped serial device mapped in the 0x80000000..0x8000ffff
range belongs to the SoC address space, thus is always mapped in
the memory bus.
Map the devices on the bus regardless a chardev is attached to it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Jan Kiszka <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 08975da9f0bfcfa654628cae71201a351ba5449a
https://github.com/qemu/qemu/commit/08975da9f0bfcfa654628cae71201a351ba5449a
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
Now that we can pass 7 parameters, do not encode register
operands within simd_data.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Taylor Simpson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694
https://github.com/qemu/qemu/commit/7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694
Author: Richard Henderson <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
DUP (indexed) can duplicate 128-bit elements, so using esz
unconditionally can assert in tcg_gen_gvec_dup_imm.
Fixes: 8711e71f9cbb
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: de2f658b6bb422ec0e0fa94a49e476018602eeea
https://github.com/qemu/qemu/commit/de2f658b6bb422ec0e0fa94a49e476018602eeea
Author: Peter Maydell <address@hidden>
Date: 2020-05-11 (Mon, 11 May 2020)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M docs/devel/loads-stores.rst
M exec.c
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2600.c
M hw/arm/musicpal.c
M hw/arm/nrf51_soc.c
M hw/i2c/microbit_i2c.c
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M hw/timer/nrf51_timer.c
M hw/timer/trace-events
M include/exec/cpu-all.h
M include/exec/cpu_ldst.h
M include/exec/exec-all.h
M include/hw/arm/nrf51.h
M include/hw/core/cpu.h
M include/hw/i2c/microbit_i2c.h
M include/hw/misc/aspeed_scu.h
M include/hw/timer/nrf51_timer.h
M target/arm/Makefile.objs
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
A target/arm/cpu_tcg.c
M target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200511'
into staging
target-arm queue:
aspeed: Add boot stub for smp booting
target/arm: Drop access_el3_aa32ns_aa64any()
aspeed: Support AST2600A1 silicon revision
aspeed: sdmc: Implement AST2600 locking behaviour
nrf51: Tracing cleanups
target/arm: Improve handling of SVE loads and stores
target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds
hw/arm/musicpal: Map the UART devices unconditionally
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
# gpg: Signature made Mon 11 May 2020 14:33:14 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200511: (34 commits)
target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed)
target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA
hw/arm/musicpal: Map the UART devices unconditionally
target/arm: Restrict TCG cpus to TCG accel
target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs
target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
target/arm: Make set_feature() available for other files
target/arm/kvm: Inline set_feature() calls
target/arm: Remove sve_memopidx
target/arm: Reuse sve_probe_page for gather loads
target/arm: Reuse sve_probe_page for scatter stores
target/arm: Reuse sve_probe_page for gather first-fault loads
target/arm: Use SVEContLdSt for contiguous stores
target/arm: Update contiguous first-fault and no-fault loads
target/arm: Use SVEContLdSt for multi-register contiguous loads
target/arm: Handle watchpoints in sve_ld1_r
target/arm: Use SVEContLdSt in sve_ld1_r
target/arm: Adjust interface of sve_ld1_host_fn
target/arm: Add sve infrastructure for page lookup
target/arm: Drop manual handling of set/clear_helper_retaddr
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/c88f1ffc19e3...de2f658b6bb4
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