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[Qemu-commits] [qemu/qemu] ac5f72: riscv: Suppress the error report for


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] ac5f72: riscv: Suppress the error report for QEMU testing ...
Date: Thu, 04 Jun 2020 04:45:28 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ac5f7246d74eecb1da1e5561d933a3c139c71c78
      
https://github.com/qemu/qemu/commit/ac5f7246d74eecb1da1e5561d933a3c139c71c78
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

We only ship plain binary bios images in the QEMU source. With Spike
machine that uses ELF images as the default bios, running QEMU test
will complain hence let's suppress the error report for QEMU testing.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <1588348254-7241-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 087a42467405de45674f76da6a72406764cde6a6
      
https://github.com/qemu/qemu/commit/087a42467405de45674f76da6a72406764cde6a6
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  riscv: Change the default behavior if no -bios option is specified

Per QEMU deprecated doc, QEMU 4.1 introduced support for the -bios
option in QEMU for RISC-V for the virt machine and sifive_u machine.
The default behavior has been that QEMU does not automatically load
any firmware if no -bios option is included.

Now 2 releases passed, it's time to change the default behavior to
load the default OpenSBI firmware automatically. The firmware is
included with the QEMU release and no user interaction is required.
All a user needs to do is specify the kernel they want to boot with
the -kernel option.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1588335545-649-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1588335545-649-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 139177b1d4d69e2a31db12ee5bdee7ef9bfe51dc
      
https://github.com/qemu/qemu/commit/139177b1d4d69e2a31db12ee5bdee7ef9bfe51dc
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions

To keep consistency with the machine* functions, remove the riscv_
prefix of the soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1590072147-13035-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1590072147-13035-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b2a3a071f76d45c7ac2b8a1640153d3cc8259ca3
      
https://github.com/qemu/qemu/commit/b2a3a071f76d45c7ac2b8a1640153d3cc8259ca3
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Remove the riscv_ prefix of the machine* functions

Remove the riscv_ prefix of the machine* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1590072147-13035-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1590072147-13035-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 26cd0362dd43a32fc9a917f5c00b20e9dafa93be
      
https://github.com/qemu/qemu/commit/26cd0362dd43a32fc9a917f5c00b20e9dafa93be
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M docs/system/deprecated.rst
    M hw/riscv/spike.c
    M include/hw/riscv/spike.h

  Log Message:
  -----------
  hw/riscv: spike: Remove deprecated ISA specific machines

The ISA specific Spike machines have been deprecated in QEMU since 4.1,
let's finally remove them.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>


  Commit: 65a117da6ec5f0226952368d544cfb5c2a1dcead
      
https://github.com/qemu/qemu/commit/65a117da6ec5f0226952368d544cfb5c2a1dcead
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M docs/system/deprecated.rst
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M tests/qtest/machine-none-test.c

  Log Message:
  -----------
  target/riscv: Remove the deprecated CPUs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 1a9540d1f1a9c5022d9273d0244e5809679dd33b
      
https://github.com/qemu/qemu/commit/1a9540d1f1a9c5022d9273d0244e5809679dd33b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M docs/system/deprecated.rst
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/monitor.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Drop support for ISA spec version 1.09.1

The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: f33559a427134ff1ae49982bdca8d10f81837204
      
https://github.com/qemu/qemu/commit/f33559a427134ff1ae49982bdca8d10f81837204
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M docs/system/deprecated.rst

  Log Message:
  -----------
  docs: deprecated: Update the -bios documentation

Update the -bios deprecation documentation to describe the new
behaviour.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 0869490b1cc4d917ac4eb3a02cac7d71149def91
      
https://github.com/qemu/qemu/commit/0869490b1cc4d917ac4eb3a02cac7d71149def91
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_e.c
    M include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  riscv: sifive_e: Manually define the machine

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>


  Commit: 757e99b1ebfa8bc2823ba686ab56bb9941b2f238
      
https://github.com/qemu/qemu/commit/757e99b1ebfa8bc2823ba686ab56bb9941b2f238
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  riscv/boot: Add a missing header include

As the functions declared in this header use the symbol_fn_t
typedef itself declared in "hw/loader.h", we need to include
it here to make the header file self-contained.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: f92d46ad07064d7b45ebb5f0e983af9b29af2ced
      
https://github.com/qemu/qemu/commit/f92d46ad07064d7b45ebb5f0e983af9b29af2ced
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Don't overwrite the reset vector

The reset vector is set in the init function don't set it again in
realize.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 8be6971b73da45e8ee9f8decd136ff054b5230ac
      
https://github.com/qemu/qemu/commit/8be6971b73da45e8ee9f8decd136ff054b5230ac
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Disable the MMU correctly

Previously if we didn't enable the MMU it would be enabled in the
realize() function anyway. Let's ensure that if we don't want the MMU we
disable it. We also don't need to enable the MMU as it will be enabled
in realize() by default.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: ff832b77aa8ab454e092fb73b61821e56218e8a5
      
https://github.com/qemu/qemu/commit/ff832b77aa8ab454e092fb73b61821e56218e8a5
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Don't set PMP feature in the cpu init

The PMP is enabled by default via the "pmp" property so there is no need
for us to set it in the init function. As all CPUs have PMP support just
remove the set_feature() call in the CPU init functions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 36b80ad99f7ea4979a4c5fc6e4072619b405e3b0
      
https://github.com/qemu/qemu/commit/36b80ad99f7ea4979a4c5fc6e4072619b405e3b0
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add the lowRISC Ibex CPU

Ibex is a small and efficient, 32-bit, in-order RISC-V core with
a 2-stage pipeline that implements the RV32IMC instruction set
architecture.

For more details on lowRISC see here:
https://github.com/lowRISC/ibex

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>


  Commit: fe0fe4735e798578097758781166cc221319b93d
      
https://github.com/qemu/qemu/commit/fe0fe4735e798578097758781166cc221319b93d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-03 (Wed, 03 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M hw/riscv/Kconfig
    M hw/riscv/Makefile.objs
    A hw/riscv/opentitan.c
    A include/hw/riscv/opentitan.h

  Log Message:
  -----------
  riscv: Initial commit of OpenTitan machine

This adds a barebone OpenTitan machine to QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 66234fee9c2d37bfbc523aa8d0ae5300a14cc10e
      
https://github.com/qemu/qemu/commit/66234fee9c2d37bfbc523aa8d0ae5300a14cc10e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-04 (Thu, 04 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M docs/system/deprecated.rst
    M hw/riscv/Kconfig
    M hw/riscv/Makefile.objs
    M hw/riscv/boot.c
    A hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    A include/hw/riscv/opentitan.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/spike.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/monitor.c
    M target/riscv/op_helper.c
    M tests/qtest/machine-none-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200603' into staging

This is a collection of RISC-V patches for 5.1.

This incldues removing deprecated features and part of the OpenTitan
support series.

# gpg: Signature made Wed 03 Jun 2020 17:12:43 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200603:
  riscv: Initial commit of OpenTitan machine
  target/riscv: Add the lowRISC Ibex CPU
  target/riscv: Don't set PMP feature in the cpu init
  target/riscv: Disable the MMU correctly
  target/riscv: Don't overwrite the reset vector
  riscv/boot: Add a missing header include
  riscv: sifive_e: Manually define the machine
  docs: deprecated: Update the -bios documentation
  target/riscv: Drop support for ISA spec version 1.09.1
  target/riscv: Remove the deprecated CPUs
  hw/riscv: spike: Remove deprecated ISA specific machines
  hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
  hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
  riscv: Change the default behavior if no -bios option is specified
  riscv: Suppress the error report for QEMU testing with riscv_find_firmware()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/5cc7a54c2e91...66234fee9c2d



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