[Qemu-commits] [qemu/qemu] 354908: riscv: Add helper to make NaN-boxing

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[Qemu-commits] [qemu/qemu] 354908: riscv: Add helper to make NaN-boxing

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 354908: riscv: Add helper to make NaN-boxing for FP register
Date:	Mon, 22 Jun 2020 08:16:30 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 354908cee1f7ff761b5fedbdb6376c378c10f941
      
https://github.com/qemu/qemu/commit/354908cee1f7ff761b5fedbdb6376c378c10f941
  Author: Ian Jiang <ianjiang.ict@gmail.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.inc.c

  Log Message:
  -----------
  riscv: Add helper to make NaN-boxing for FP register

The function that makes NaN-boxing when a 32-bit value is assigned
to a 64-bit FP register is split out to a helper gen_nanbox_fpr().
Then it is applied in translating of the FLW instruction.

Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Message-Id: <20200128003707.17028-1-ianjiang.ict@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1
      
https://github.com/qemu/qemu/commit/5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_e.c
    M include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  sifive_e: Support the revB machine

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e7b5dfd34f296db56aa5de31d1cf64dbe82674a3
      
https://github.com/qemu/qemu/commit/e7b5dfd34f296db56aa5de31d1cf64dbe82674a3
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  riscv: Generalize CPU init routine for the base CPU

There is no need to have two functions that have exactly the same
codes for 32-bit and 64-bit base CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4c56793f59b9a1513868e11fd87c5d6e4a5e8edd
      
https://github.com/qemu/qemu/commit/4c56793f59b9a1513868e11fd87c5d6e4a5e8edd
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  riscv: Generalize CPU init routine for the gcsu CPU

There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit gcsu CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d8e72bd1613d4fcae10fd7409fc90cb3586714d1
      
https://github.com/qemu/qemu/commit/d8e72bd1613d4fcae10fd7409fc90cb3586714d1
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  riscv: Generalize CPU init routine for the imacu CPU

There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit imacu CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2fdd2c094a3df68084df07de99ac5f7316c54145
      
https://github.com/qemu/qemu/commit/2fdd2c094a3df68084df07de99ac5f7316c54145
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  riscv: Keep the CPU init routine names consistent

Adding a _ to keep some consistency among the CPU init routines.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: efe9f9c820d1322729957a60ff785c9527a79ddf
      
https://github.com/qemu/qemu/commit/efe9f9c820d1322729957a60ff785c9527a79ddf
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Set access as data_load when validating stage-2 PTEs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 88914473e748db20d8e18b9735f647a683319fa6
      
https://github.com/qemu/qemu/commit/88914473e748db20d8e18b9735f647a683319fa6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Report errors validating 2nd-stage PTEs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b8429ded723ec52568e05f6a24ed78c93224687c
      
https://github.com/qemu/qemu/commit/b8429ded723ec52568e05f6a24ed78c93224687c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c
    A target/riscv/insn_trans/trans_rvh.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Move the hfence instructions to the rvh decode

Also correct the name of the VVMA instruction.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2761db5fc20943bbd606b6fd49640ac000398de6
      
https://github.com/qemu/qemu/commit/2761db5fc20943bbd606b6fd49640ac000398de6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_rvh.inc.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Implement checks for hfence

Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 888c9af23ff0fced10a58041e6658e0eb60143cb
      
https://github.com/qemu/qemu/commit/888c9af23ff0fced10a58041e6658e0eb60143cb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  riscv/opentitan: Fix the ROM size

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Damien Hedde <damien.hedde@greensocs.com>


  Commit: a7d2d98c5944cec9ac8ed12215c2ea9d4545779b
      
https://github.com/qemu/qemu/commit/a7d2d98c5944cec9ac8ed12215c2ea9d4545779b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M hw/char/Makefile.objs
    A hw/char/ibex_uart.c
    M hw/riscv/Kconfig
    A include/hw/char/ibex_uart.h

  Log Message:
  -----------
  hw/char: Initial commit of Ibex UART

This is the initial commit of the Ibex UART device. Serial TX is
working, while RX has been implemeneted but untested.

This is based on the documentation from:
https://docs.opentitan.org/hw/ip/uart/doc/

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>


  Commit: 879f60f01c1c655676207ea73d9250a7bc4a915f
      
https://github.com/qemu/qemu/commit/879f60f01c1c655676207ea73d9250a7bc4a915f
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M hw/intc/Makefile.objs
    A hw/intc/ibex_plic.c
    A include/hw/intc/ibex_plic.h

  Log Message:
  -----------
  hw/intc: Initial commit of lowRISC Ibex PLIC

The Ibex core contains a PLIC that although similar to the RISC-V spec
is not RISC-V spec compliant.

This patch implements a Ibex PLIC in a somewhat generic way.

As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex
PLIC move towards spec compliance this PLIC implementation can be
updated until it can replace the current PLIC.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>


  Commit: b9fc51354cdc8e2623925c8fd76d7634240a28af
      
https://github.com/qemu/qemu/commit/b9fc51354cdc8e2623925c8fd76d7634240a28af
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  riscv/opentitan: Connect the PLIC device

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: cc4112605eaf5aebbe186469eba790ac1562b3ef
      
https://github.com/qemu/qemu/commit/cc4112605eaf5aebbe186469eba790ac1562b3ef
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  riscv/opentitan: Connect the UART device

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 1145188e091aa4675b09882b6bd500c50b87547f
      
https://github.com/qemu/qemu/commit/1145188e091aa4675b09882b6bd500c50b87547f
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Use a smaller guess size for no-MMU PMP

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>


  Commit: 8f8c6c1a6420483af93fe1fbeb14c5aa8f104c8d
      
https://github.com/qemu/qemu/commit/8f8c6c1a6420483af93fe1fbeb14c5aa8f104c8d
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* 
functions

This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 894944624bd986383ff403368bdae902ec97cc57
      
https://github.com/qemu/qemu/commit/894944624bd986383ff403368bdae902ec97cc57
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* 
functions

This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5874f0a7155e262e96c91ed60b5f728f592cd516
      
https://github.com/qemu/qemu/commit/5874f0a7155e262e96c91ed60b5f728f592cd516
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit

There is no need to retrieve all PLIC IRQ information in order to
just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
what is done for other peripherals.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-4-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ea85f27d4123b97e0f2a58d2ed3b5215bf93bab4
      
https://github.com/qemu/qemu/commit/ea85f27d4123b97e0f2a58d2ed3b5215bf93bab4
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Generate device tree node for OTP

Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
based on device tree information. Let's generate the device tree
node for OTP.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2e30ccb425fafa7b7b76d41a7f2e97dd6977fbce
      
https://github.com/qemu/qemu/commit/2e30ccb425fafa7b7b76d41a7f2e97dd6977fbce
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_gpio.c
    M include/hw/riscv/sifive_gpio.h

  Log Message:
  -----------
  hw/riscv: sifive_gpio: Clean up the codes

Do various minor clean-ups to the exisiting codes for:

- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4bb216f637d16b6deed499d0be1c34ff03bd625c
      
https://github.com/qemu/qemu/commit/4bb216f637d16b6deed499d0be1c34ff03bd625c
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_gpio.c
    M include/hw/riscv/sifive_gpio.h

  Log Message:
  -----------
  hw/riscv: sifive_gpio: Add a new 'ngpio' property

Add a new property to represent the number of GPIO pins supported
by the GPIO controller.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-7-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8a88b9f54f5fb2acecf73760903b1f58fb40d0cd
      
https://github.com/qemu/qemu/commit/8a88b9f54f5fb2acecf73760903b1f58fb40d0cd
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Hook a GPIO controller

SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
This hooks the exsiting SiFive GPIO model to the SoC, and adds its
device tree data as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 621c1006d2d82da9f266f21ad8e887c38769a11b
      
https://github.com/qemu/qemu/commit/621c1006d2d82da9f266f21ad8e887c38769a11b
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_gpio.c

  Log Message:
  -----------
  hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5133ed17906d1116c7ce47fd49ae77373cd41e29
      
https://github.com/qemu/qemu/commit/5133ed17906d1116c7ce47fd49ae77373cd41e29
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Add reset functionality

The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-10-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3e9667cdaa7d552bad232b7da0e116c50e15b3b5
      
https://github.com/qemu/qemu/commit/3e9667cdaa7d552bad232b7da0e116c50e15b3b5
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Rename serial property get/set functions to a generic name

In prepration to add more properties to this machine, rename the
existing serial property get/set functions to a generic name.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-11-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cfa32630d914373413c0b42faf756ccaabc4bbb9
      
https://github.com/qemu/qemu/commit/cfa32630d914373413c0b42faf756ccaabc4bbb9
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Add a new property msel for MSEL pin state

On SiFive FU540 SoC, the value stored at physical address 0x1000
stores the MSEL pin state that is used to control the next boot
location that ROM codes jump to.

Add a new property msel to sifive_u machine for this.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com
Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e8905c6ce86f5023f6814abd7c72a809e5d018ec
      
https://github.com/qemu/qemu/commit/e8905c6ce86f5023f6814abd7c72a809e5d018ec
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Rename IBEX CPU init routine

Current IBEX CPU init routine name seems to be too generic.
Since it uses a different reset vector from the generic one,
it merits a dedicated name.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 495134b75cca3e6a34d4233113c5143439061771
      
https://github.com/qemu/qemu/commit/495134b75cca3e6a34d4233113c5143439061771
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M target/riscv/cpu.c

  Log Message:
  -----------
  hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 17aad9f276953c1eaf0750faf4758fd2f5ebeb84
      
https://github.com/qemu/qemu/commit/17aad9f276953c1eaf0750faf4758fd2f5ebeb84
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Support different boot source per MSEL pin state

SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.

The SoC supports booting from memory-mapped QSPI flash, which is
how start_in_flash property is used for at present. This matches
MSEL = 1 configuration (QSPI0).

Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
It's not necessary for QEMU to implement the full ZSBL ROM codes,
because we know ZSBL downloads the next stage program into the L2
LIM at address 0x8000000 and executes from there. We can bypass
the whole ZSBL execution and use "-bios" to load the next stage
program directly if MSEL indicates a ZSBL booting flow.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 49093916d37f663e86316ec54cb77d5515bb973f
      
https://github.com/qemu/qemu/commit/49093916d37f663e86316ec54cb77d5515bb973f
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Sort the SoC memmap table entries

Move the flash and DRAM to the end of the SoC memmap table.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3eaea6eb4e534f7b87c6eca808149bb671976800
      
https://github.com/qemu/qemu/commit/3eaea6eb4e534f7b87c6eca808149bb671976800
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-06-19 (Fri, 19 Jun 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Add a dummy DDR memory controller device

It is enough to simply map the SiFive FU540 DDR memory controller
into the MMIO space using create_unimplemented_device(), to make
the upstream U-Boot v2020.07 DDR memory initialization codes happy.

Note we do not generate device tree fragment for the DDR memory
controller. Since the controller data in device tree consumes a
very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
U-Boot source), and it is only needed by U-Boot SPL but not any
operating system, we choose not to generate the fragment here.
This also means when testing with U-Boot SPL, the device tree has
to come from U-Boot SPL itself, but not the one generated by QEMU
on the fly. The memory has to be set to 8GiB to match the real
HiFive Unleashed board when invoking QEMU (-m 8G).

With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:

$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin

U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014

The above exception is expected because QSPI is unsupported yet.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-6-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 171199f56f5f9bdf1e5d670d09ef1351d8f01bae
      
https://github.com/qemu/qemu/commit/171199f56f5f9bdf1e5d670d09ef1351d8f01bae
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-22 (Mon, 22 Jun 2020)

  Changed paths:
    M MAINTAINERS
    M hw/char/Makefile.objs
    A hw/char/ibex_uart.c
    M hw/intc/Makefile.objs
    A hw/intc/ibex_plic.c
    M hw/riscv/Kconfig
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_gpio.c
    M hw/riscv/sifive_u.c
    A include/hw/char/ibex_uart.h
    A include/hw/intc/ibex_plic.h
    M include/hw/riscv/opentitan.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_gpio.h
    M include/hw/riscv/sifive_u.h
    M target/riscv/cpu.c
    M target/riscv/cpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/insn_trans/trans_rvf.inc.c
    A target/riscv/insn_trans/trans_rvh.inc.c
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200619-3' into staging

This is a range of patches for RISC-V.

Some key points are:
 - Generalise the CPU init functions
 - Support the SiFive revB machine
 - Improvements to the Hypervisor implementation and error checking
 - Connect some OpenTitan devices
 - Changes to the sifive_u machine to support U-boot

v2:
 - Fix missing realise assert

# gpg: Signature made Fri 19 Jun 2020 17:34:34 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200619-3: (32 commits)
  hw/riscv: sifive_u: Add a dummy DDR memory controller device
  hw/riscv: sifive_u: Sort the SoC memmap table entries
  hw/riscv: sifive_u: Support different boot source per MSEL pin state
  hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
  target/riscv: Rename IBEX CPU init routine
  hw/riscv: sifive_u: Add a new property msel for MSEL pin state
  hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
  hw/riscv: sifive_u: Add reset functionality
  hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
  hw/riscv: sifive_u: Hook a GPIO controller
  hw/riscv: sifive_gpio: Add a new 'ngpio' property
  hw/riscv: sifive_gpio: Clean up the codes
  hw/riscv: sifive_u: Generate device tree node for OTP
  hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
  hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* 
functions
  hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* 
functions
  target/riscv: Use a smaller guess size for no-MMU PMP
  riscv/opentitan: Connect the UART device
  riscv/opentitan: Connect the PLIC device
  hw/intc: Initial commit of lowRISC Ibex PLIC
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/bae31bfa48b9...171199f56f5f
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