[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] ec729c: target/mips: Add CP0 Config0 register
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] ec729c: target/mips: Add CP0 Config0 register definitions ... |
|
Date: |
Fri, 08 Jan 2021 02:44:03 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ec729cd617d02b6dde1fc19de0c00b18be3c56ec
https://github.com/qemu/qemu/commit/ec729cd617d02b6dde1fc19de0c00b18be3c56ec
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
Commit: f4ab122590c0ef704caaa8c761ec00428bfdbb11
https://github.com/qemu/qemu/commit/f4ab122590c0ef704caaa8c761ec00428bfdbb11
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Replace CP0_Config0 magic values by proper definitions
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
Commit: ddaa112daffe0b95bd7f8c95ac6848b960f9d6fc
https://github.com/qemu/qemu/commit/ddaa112daffe0b95bd7f8c95ac6848b960f9d6fc
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/addr.c
M target/mips/cpu.h
Log Message:
-----------
target/mips/addr: Add translation helpers for KSEG1
It's useful for bootloader to do I/O operations.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: ea06276496568e5c3864b73c42f36f3c9b654147
https://github.com/qemu/qemu/commit/ea06276496568e5c3864b73c42f36f3c9b654147
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
Commit: ca188270534775a5e7378c3fd3c4168eca66196e
https://github.com/qemu/qemu/commit/ca188270534775a5e7378c3fd3c4168eca66196e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Reorder CPU_MIPS5 definition
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
Commit: b8afefeeb0288b6556562acf600349bd6a909512
https://github.com/qemu/qemu/commit/b8afefeeb0288b6556562acf600349bd6a909512
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
Commit: 0857ea9ec9fc7714785f275c3aa0696a59a9bd50
https://github.com/qemu/qemu/commit/0857ea9ec9fc7714785f275c3aa0696a59a9bd50
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu.h
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
Commit: 37653f68ca37537311ad110cecf9e4a46e0513be
https://github.com/qemu/qemu/commit/37653f68ca37537311ad110cecf9e4a46e0513be
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-6-f4bug@amsat.org>
Commit: 9f66379fc8405f2b371f02181290bf53c297031a
https://github.com/qemu/qemu/commit/9f66379fc8405f2b371f02181290bf53c297031a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
Commit: c4f64f034522b50447eb004de8ba3cebdba48204
https://github.com/qemu/qemu/commit/c4f64f034522b50447eb004de8ba3cebdba48204
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
Commit: 4d2140e39c2c240b2e21811c58f7080fa817bfa4
https://github.com/qemu/qemu/commit/4d2140e39c2c240b2e21811c58f7080fa817bfa4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
Commit: a4e8bd844fea23b92d92c7b4dbab32d99d4d8b84
https://github.com/qemu/qemu/commit/a4e8bd844fea23b92d92c7b4dbab32d99d4d8b84
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
Commit: 1c2bb63c27fd2681fd48cdf9345a88cbe752baa9
https://github.com/qemu/qemu/commit/1c2bb63c27fd2681fd48cdf9345a88cbe752baa9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
Commit: 0d0754d4774e767081fe2100135d0550a47d4d63
https://github.com/qemu/qemu/commit/0d0754d4774e767081fe2100135d0550a47d4d63
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
Commit: 34985753f1bb5abe4eb49563d5bdd5ed8ad0bb80
https://github.com/qemu/qemu/commit/34985753f1bb5abe4eb49563d5bdd5ed8ad0bb80
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/cp0_timer.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
Commit: b15c3aab6caf435c85059892223401ed5b61f662
https://github.com/qemu/qemu/commit/b15c3aab6caf435c85059892223401ed5b61f662
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-14-f4bug@amsat.org>
Commit: 28f24e18724d7b0985874b76ad84fad104a7cc9c
https://github.com/qemu/qemu/commit/28f24e18724d7b0985874b76ad84fad104a7cc9c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
Commit: 162c57ce6887d4c170eab23045bab5e00bf691b0
https://github.com/qemu/qemu/commit/162c57ce6887d4c170eab23045bab5e00bf691b0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/cp0_helper.c
M target/mips/cpu.c
M target/mips/fpu_helper.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
Commit: fd2e002d2e77f0875456bcc3e6a78b00d9dd05f2
https://github.com/qemu/qemu/commit/fd2e002d2e77f0875456bcc3e6a78b00d9dd05f2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-2-f4bug@amsat.org>
Commit: 4df0c2d38952d76535011ff590f147cc1add6af7
https://github.com/qemu/qemu/commit/4df0c2d38952d76535011ff590f147cc1add6af7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/fpu_helper.c
A target/mips/fpu_helper.h
M target/mips/gdbstub.c
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/machine.c
M target/mips/msa_helper.c
M target/mips/op_helper.c
M target/mips/translate.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
Commit: 9a6e05d27164e44476a7f28d6627ccc81bd3d880
https://github.com/qemu/qemu/commit/9a6e05d27164e44476a7f28d6627ccc81bd3d880
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/helper.c
Log Message:
-----------
target/mips: Add !CONFIG_USER_ONLY comment after #endif
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
Commit: c085a8b80582224ec952f7bbe4fe21fe20ef6f71
https://github.com/qemu/qemu/commit/c085a8b80582224ec952f7bbe4fe21fe20ef6f71
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/helper.c
Log Message:
-----------
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-5-f4bug@amsat.org>
Commit: a4262ee2866019e19b16c7bc5f1b3134a8c58c9e
https://github.com/qemu/qemu/commit/a4262ee2866019e19b16c7bc5f1b3134a8c58c9e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/helper.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Move common helpers from helper.c to cpu.c
The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
Commit: 6657f45ccdd452219316c23150476a97ecd9a18b
https://github.com/qemu/qemu/commit/6657f45ccdd452219316c23150476a97ecd9a18b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
R target/mips/helper.c
M target/mips/meson.build
A target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Rename helper.c as tlb_helper.c
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
Commit: 745b04b7849d744da51068701066c00d26958165
https://github.com/qemu/qemu/commit/745b04b7849d744da51068701066c00d26958165
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Fix code style for checkpatch.pl
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
Commit: b05eeb25487481a83e90b5a7c7885ce73c89a76e
https://github.com/qemu/qemu/commit/b05eeb25487481a83e90b5a7c7885ce73c89a76e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tlb_helper.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Move mmu_init() functions to tlb_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
Commit: 670777c9f19f3701e93d1c8d238f887fb1cb6e75
https://github.com/qemu/qemu/commit/670777c9f19f3701e93d1c8d238f887fb1cb6e75
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
A target/mips/cpu-defs.c.inc
M target/mips/cpu.c
R target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Rename translate_init.c as cpu-defs.c
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-10-f4bug@amsat.org>
Commit: 33ef6aa81e8295a6ca1e934229c8806e8da231f4
https://github.com/qemu/qemu/commit/33ef6aa81e8295a6ca1e934229c8806e8da231f4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
A target/mips/translate.h
Log Message:
-----------
target/mips/translate: Extract DisasContext structure
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
Commit: e549850535924e2631b848673e2b28195c2856f2
https://github.com/qemu/qemu/commit/e549850535924e2631b848673e2b28195c2856f2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips/translate: Add declarations for generic code
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
Commit: 112fe13d22c89525719abf729e559663bba2557f
https://github.com/qemu/qemu/commit/112fe13d22c89525719abf729e559663bba2557f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
Commit: 2e37dd0aeb1ef1e1f2b3900b12f83f0952bb40a6
https://github.com/qemu/qemu/commit/2e37dd0aeb1ef1e1f2b3900b12f83f0952bb40a6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-12-f4bug@amsat.org>
Commit: 54cd5f5860e3e21b57e33bf778a141a48c3f7d2d
https://github.com/qemu/qemu/commit/54cd5f5860e3e21b57e33bf778a141a48c3f7d2d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Declare generic FPU functions in 'translate.h'
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
Commit: d7e46eba0342e8d6c65ea72b130b24797953f204
https://github.com/qemu/qemu/commit/d7e46eba0342e8d6c65ea72b130b24797953f204
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Extract FPU specific definitions to translate.h
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-16-f4bug@amsat.org>
Commit: 884537d7ca3cae984cb40739d3911909cb3aed31
https://github.com/qemu/qemu/commit/884537d7ca3cae984cb40739d3911909cb3aed31
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
Log Message:
-----------
target/mips: Only build TCG code when CONFIG_TCG is set
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
Commit: 51eec6ed8aaaedba8a9f6ceff5a5a6dcd1cac7bc
https://github.com/qemu/qemu/commit/51eec6ed8aaaedba8a9f6ceff5a5a6dcd1cac7bc
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
Commit: 968d840d77a403d141c7f9fb14c9543e8f9b6324
https://github.com/qemu/qemu/commit/968d840d77a403d141c7f9fb14c9543e8f9b6324
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
Commit: 404eb562cb5aaaf99a99f9d5129a27bfe691328f
https://github.com/qemu/qemu/commit/404eb562cb5aaaf99a99f9d5129a27bfe691328f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/kvm.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Introduce ase_msa_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
Commit: 026eddff4196901db058bd0b4ec8cb5d03b29bba
https://github.com/qemu/qemu/commit/026eddff4196901db058bd0b4ec8cb5d03b29bba
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
Log Message:
-----------
target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
Commit: e59c51b9f4407a4c0b1f9b5a8bbbe5f44a03a87d
https://github.com/qemu/qemu/commit/e59c51b9f4407a4c0b1f9b5a8bbbe5f44a03a87d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/internal.h
Log Message:
-----------
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-4-f4bug@amsat.org>
Commit: 6ef8a6aa7c83c613bcbda7cd80f6c050c4d3c9c9
https://github.com/qemu/qemu/commit/6ef8a6aa7c83c613bcbda7cd80f6c050c4d3c9c9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Simplify MSA TCG logic
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-5-f4bug@amsat.org>
Commit: 93ef1e7813a8d898d37389f325f0d45571ba8d21
https://github.com/qemu/qemu/commit/93ef1e7813a8d898d37389f325f0d45571ba8d21
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Remove now unused ASE_MSA definition
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-6-f4bug@amsat.org>
Commit: 4e56d833d9bad5f2628f509b48894961c90f9dfd
https://github.com/qemu/qemu/commit/4e56d833d9bad5f2628f509b48894961c90f9dfd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Alias MSA vector registers on FPU scalar registers
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.
Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-7-f4bug@amsat.org>
Commit: d29bd93d21a6654661a91a298bd8de23e6c0c556
https://github.com/qemu/qemu/commit/d29bd93d21a6654661a91a298bd8de23e6c0c556
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Extract msa_translate_init() from mips_tcg_init()
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic initialization. We will later move this
function along with the MSA registers to the new C unit.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-8-f4bug@amsat.org>
Commit: ae60317dc7f7867f09ad2af8315c128331181f48
https://github.com/qemu/qemu/commit/ae60317dc7f7867f09ad2af8315c128331181f48
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-9-f4bug@amsat.org>
Commit: af517fcee54cc89291ec91060cccf705fd8550e4
https://github.com/qemu/qemu/commit/af517fcee54cc89291ec91060cccf705fd8550e4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-10-f4bug@amsat.org>
Commit: f7890b725b2d812c8aa0a616482cdeb47cd61675
https://github.com/qemu/qemu/commit/f7890b725b2d812c8aa0a616482cdeb47cd61675
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/msa_helper.c
Log Message:
-----------
target/mips: Move msa_reset() to msa_helper.c
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-15-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 10dbcc56f676f8321e13b3863f646bd72cdca192
https://github.com/qemu/qemu/commit/10dbcc56f676f8321e13b3863f646bd72cdca192
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/msa_helper.c
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Extract MSA helpers from op_helper.c
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 1061bf6430af62831876e722cd7b70bc3d6218e7
https://github.com/qemu/qemu/commit/1061bf6430af62831876e722cd7b70bc3d6218e7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/helper.h
A target/mips/msa_helper.h.inc
Log Message:
-----------
target/mips: Extract MSA helper definitions
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-4-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: c6bf9f4f6abf4d4d0281ee6590fdf521915011ba
https://github.com/qemu/qemu/commit/c6bf9f4f6abf4d4d0281ee6590fdf521915011ba
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Declare gen_msa/_branch() in 'translate.h'
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-18-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: e26a84d83fbf8e603901d6ae04d4251e6b094c44
https://github.com/qemu/qemu/commit/e26a84d83fbf8e603901d6ae04d4251e6b094c44
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/msa_translate.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Extract MSA translation routines
Extract 2200 lines from the huge translate.c to a new file,
'msa_translate.c'. As there are too many inter-dependencies
we don't compile it as another object yet, but keep including
it in the big translate.o. We gain in code maintainability.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 586bbba9aba247f2f61c51d817f8f011a5cd5ee8
https://github.com/qemu/qemu/commit/586bbba9aba247f2f61c51d817f8f011a5cd5ee8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/msa_translate.c
Log Message:
-----------
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-25-f4bug@amsat.org>
Commit: 1d17e88075762ba1bc32f3ace57cf4559ce4e188
https://github.com/qemu/qemu/commit/1d17e88075762ba1bc32f3ace57cf4559ce4e188
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/msa32.decode
M target/mips/msa_translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-20-f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 433f6795f4e465b9588da558a0a59dca50655de6
https://github.com/qemu/qemu/commit/433f6795f4e465b9588da558a0a59dca50655de6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/msa_translate.c
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Use decode_ase_msa() generated from decodetree
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: fd396ddeb637a1e4021bbe4f901a2a77297cc9f9
https://github.com/qemu/qemu/commit/fd396ddeb637a1e4021bbe4f901a2a77297cc9f9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
M target/mips/translate.c
M target/mips/translate.h
A target/mips/translate_addr_const.c
Log Message:
-----------
target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
Commit: 93ff47916057ed74a49fc1989f5a8f14dfe69d39
https://github.com/qemu/qemu/commit/93ff47916057ed74a49fc1989f5a8f14dfe69d39
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
M target/mips/msa32.decode
A target/mips/msa64.decode
M target/mips/msa_translate.c
Log Message:
-----------
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-23-f4bug@amsat.org>
Commit: b4bec09a53bb4dbce1f544c954f40dc6a18a4df2
https://github.com/qemu/qemu/commit/b4bec09a53bb4dbce1f544c954f40dc6a18a4df2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/mips32r6.decode
A target/mips/mips64r6.decode
A target/mips/rel6_translate.c
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
Commit: 6597b555d11159b1efbae38c74e2b779c6e96491
https://github.com/qemu/qemu/commit/6597b555d11159b1efbae38c74e2b779c6e96491
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
Commit: 58d8597d8af9a6c00d9beafbd0eec9f97013737c
https://github.com/qemu/qemu/commit/58d8597d8af9a6c00d9beafbd0eec9f97013737c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/rel6_translate.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 Special2 opcode to decodetree
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
Commit: 8d459feac5820ff25ed58c569e20dda67a4e422c
https://github.com/qemu/qemu/commit/8d459feac5820ff25ed58c569e20dda67a4e422c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 COP1X opcode to decodetree
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
Commit: c6a492d1f72c33c1ee9a71ab54493437ae82c60e
https://github.com/qemu/qemu/commit/c6a492d1f72c33c1ee9a71ab54493437ae82c60e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
Commit: 82aa4978a06bdcc54957e533de4e50f899aff329
https://github.com/qemu/qemu/commit/82aa4978a06bdcc54957e533de4e50f899aff329
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
Commit: e02a714f7503bb186489ecab9172ede71dccecca
https://github.com/qemu/qemu/commit/e02a714f7503bb186489ecab9172ede71dccecca
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
Commit: 76903ffdcb62f64ce44fdbbd920014b50bc332c7
https://github.com/qemu/qemu/commit/76903ffdcb62f64ce44fdbbd920014b50bc332c7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips64r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
Commit: 0950b6a28bf62ee623aa808186a7aec20f2bf6a4
https://github.com/qemu/qemu/commit/0950b6a28bf62ee623aa808186a7aec20f2bf6a4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips64r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-13-f4bug@amsat.org>
Commit: 9d481cfddd4c5f2c2b5f697f737ad49ad4464396
https://github.com/qemu/qemu/commit/9d481cfddd4c5f2c2b5f697f737ad49ad4464396
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LL/SC opcodes to decodetree
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
Commit: f97d339d612b86d8d336a11f01719a10893d6707
https://github.com/qemu/qemu/commit/f97d339d612b86d8d336a11f01719a10893d6707
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-07 (Thu, 07 Jan 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M hw/mips/fuloong2e.c
Log Message:
-----------
docs/system: Remove deprecated 'fulong2e' machine alias
The 'fulong2e' machine alias has been marked as deprecated since
QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
Time to remove it now.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20210106184602.3771551-1-f4bug@amsat.org>
Commit: 377d542e393ef49a04d187b7b09409e4512e4a91
https://github.com/qemu/qemu/commit/377d542e393ef49a04d187b7b09409e4512e4a91
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-01-08 (Fri, 08 Jan 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M linux-user/mips/cpu_loop.c
M target/mips/addr.c
M target/mips/cp0_helper.c
M target/mips/cp0_timer.c
A target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/fpu_helper.c
A target/mips/fpu_helper.h
M target/mips/gdbstub.c
R target/mips/helper.c
M target/mips/helper.h
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/machine.c
M target/mips/meson.build
M target/mips/mips-defs.h
A target/mips/mips32r6.decode
A target/mips/mips64r6.decode
A target/mips/msa32.decode
A target/mips/msa64.decode
M target/mips/msa_helper.c
A target/mips/msa_helper.h.inc
A target/mips/msa_translate.c
M target/mips/op_helper.c
A target/mips/rel6_translate.c
A target/mips/tlb_helper.c
M target/mips/translate.c
A target/mips/translate.h
A target/mips/translate_addr_const.c
R target/mips/translate_init.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210107' into
staging
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
# gpg: Signature made Thu 07 Jan 2021 22:20:57 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-20210107: (66 commits)
docs/system: Remove deprecated 'fulong2e' machine alias
target/mips: Convert Rel6 LL/SC opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Extract LSA/DLSA translation generators
target/mips: Use decode_ase_msa() generated from decodetree
target/mips: Introduce decode tree bindings for MSA ASE
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
target/mips: Extract MSA translation routines
target/mips: Declare gen_msa/_branch() in 'translate.h'
target/mips: Extract MSA helper definitions
target/mips: Extract MSA helpers from op_helper.c
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e79de63ab1bd...377d542e393e
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] ec729c: target/mips: Add CP0 Config0 register definitions ...,
Peter Maydell <=