[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 0c38f6: hw/arm/virt-acpi-build: Fix GSIV valu
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 0c38f6: hw/arm/virt-acpi-build: Fix GSIV values of the {GE... |
|
Date: |
Mon, 12 Apr 2021 07:51:01 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0c38f607836af40921ea2b58676b7c4a9fe33bef
https://github.com/qemu/qemu/commit/0c38f607836af40921ea2b58676b7c4a9fe33bef
Author: Zenghui Yu <yuzenghui@huawei.com>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 017a913af4dff47ac5e62be613b9f8b88fc8fa96
https://github.com/qemu/qemu/commit/017a913af4dff47ac5e62be613b9f8b88fc8fa96
Author: Zenghui Yu <yuzenghui@huawei.com>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
start of the invalidation range, regardless of whatever the Range is,
whilst the spec clearly states that
- "Invalidation is performed for an *aligned* range of 2^(Range+1)
StreamIDs."
- "The bottom Range+1 bits of the StreamID parameter are IGNORED,
aligning the range to its size."
Take CFGI_ALL (where Range == 31) as an example, if there are some random
bits in the StreamID field, we'll fail to perform the full invalidation but
get a strange range (e.g., SMMUSIDRange={.start=1, .end=0}) instead. Rework
the emulation a bit to get rid of the discrepancy with the spec.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402100449.528-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eb42297a59e103500bdd2c352c5b52f54b1c33cd
https://github.com/qemu/qemu/commit/eb42297a59e103500bdd2c352c5b52f54b1c33cd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M accel/tcg/translate-all.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-6.c
M tests/tcg/aarch64/mte.h
Log Message:
-----------
accel/tcg: Preserve PAGE_ANON when changing page permissions
Using mprotect() to change PROT_* does not change the MAP_ANON
previously set with mmap(). Our linux-user version of MTE only
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
stop working.
Reported-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ff38bca7d633868ac094ef86f3b246e8f57181d4
https://github.com/qemu/qemu/commit/ff38bca7d633868ac094ef86f3b246e8f57181d4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Check PAGE_WRITE_ORG for MTE writeability
We can remove PAGE_WRITE when (internally) marking a page
read-only because it contains translated code.
This can be triggered by tests/tcg/aarch64/bti-2, after
having serviced SIGILL trampolines on the stack.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 52c01ada86611136e3122dd139788dbcbc292d86
https://github.com/qemu/qemu/commit/52c01ada86611136e3122dd139788dbcbc292d86
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M include/exec/cpu-all.h
Log Message:
-----------
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
Unfortuately, the elements of PAGE_* were not in numerical
order and so PAGE_ANON was added to an "unused" bit.
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
Cc: Laurent Vivier <laurent@vivier.eu>
Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
Buglink: https://bugs.launchpad.net/bugs/1922617
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620
https://github.com/qemu/qemu/commit/c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-12 (Mon, 12 Apr 2021)
Changed paths:
M accel/tcg/translate-all.c
M hw/arm/smmuv3.c
M hw/arm/virt-acpi-build.c
M include/exec/cpu-all.h
M target/arm/mte_helper.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-6.c
M tests/tcg/aarch64/mte.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412'
into staging
target-arm queue:
* hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
* hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
* accel/tcg: Preserve PAGE_ANON when changing page permissions
* target/arm: Check PAGE_WRITE_ORG for MTE writeability
* exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
# gpg: Signature made Mon 12 Apr 2021 11:31:15 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210412:
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
target/arm: Check PAGE_WRITE_ORG for MTE writeability
accel/tcg: Preserve PAGE_ANON when changing page permissions
hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f2afdc2ad94b...c1e90def01bd