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[Qemu-commits] [qemu/qemu] d7a316: target/i386: add missing bits to CR4_
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] d7a316: target/i386: add missing bits to CR4_RESERVED_MASK |
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Date: |
Wed, 08 Sep 2021 05:32:02 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: d7a316bbd298b4b4772355e373c890c0c3901f6c
https://github.com/qemu/qemu/commit/d7a316bbd298b4b4772355e373c890c0c3901f6c
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: add missing bits to CR4_RESERVED_MASK
Booting Fedora kernels with -cpu max hangs very early in boot. Disabling
the la57 CPUID bit fixes the problem. git bisect traced the regression to
commit 213ff024a2f92020290296cb9dc29c2af3d4a221 (HEAD, refs/bisect/bad)
Author: Lara Lazier <laramglazier@gmail.com>
Date: Wed Jul 21 17:26:50 2021 +0200
target/i386: Added consistency checks for CR4
All MBZ bits in CR4 must be zero. (APM2 15.5)
Added reserved bitmask and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210721152651.14683-2-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In this commit CR4_RESERVED_MASK is missing CR4_LA57_MASK and
two others. Adding this lets Fedora kernels boot once again.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Message-Id: <20210831175033.175584-1-berrange@redhat.com>
[Removed VMXE/SMXE, matching the commit message. - Paolo]
Fixes: 213ff024a2 ("target/i386: Added consistency checks for CR4", 2021-07-22)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 82e03e714b790310ff328e4ca43d0c28ed02bcdf
https://github.com/qemu/qemu/commit/82e03e714b790310ff328e4ca43d0c28ed02bcdf
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: VMRUN and VMLOAD canonicalizations
APM2 requires that VMRUN and VMLOAD canonicalize (sign extend to 63
from 48/57) all base addresses in the segment registers that have been
respectively loaded.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210804113058.45186-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b1fabf30bad7d1ee8109753b053b49976799d016
https://github.com/qemu/qemu/commit/b1fabf30bad7d1ee8109753b053b49976799d016
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/svm.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF feature
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210730070742.9674-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7a830a36d97f0f338312a11632924dec6b45bf11
https://github.com/qemu/qemu/commit/7a830a36d97f0f338312a11632924dec6b45bf11
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/machine.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Moved int_ctl into CPUX86State structure
Moved int_ctl into the CPUX86State structure. It removes some
unnecessary stores and loads, and prepares for tracking the vIRQ
state even when it is masked due to vGIF.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 18ea2e08bb8ad1b9402076bf9adb8347c77ab3cf
https://github.com/qemu/qemu/commit/18ea2e08bb8ad1b9402076bf9adb8347c77ab3cf
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF V_IRQ masking capability
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: fe8117526b7e410cc745b3b21f710024d6f617ef
https://github.com/qemu/qemu/commit/fe8117526b7e410cc745b3b21f710024d6f617ef
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added ignore TPR check in ctl_has_irq
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: faa81424b33cc3569d439ee355b89b1c5efe519a
https://github.com/qemu/qemu/commit/faa81424b33cc3569d439ee355b89b1c5efe519a
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added changed priority check for VIRQ
Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 68c7c9bacea2f0ad123e79cb645713a8e8657e73
https://github.com/qemu/qemu/commit/68c7c9bacea2f0ad123e79cb645713a8e8657e73
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/svm.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added vVMLOAD and vVMSAVE feature
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode
without
causing a VMEXIT. (APM2 15.33.1)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9c4e66df24233f860df19032f314469e072d013a
https://github.com/qemu/qemu/commit/9c4e66df24233f860df19032f314469e072d013a
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/vfio/common.c
M include/exec/memory.h
M softmmu/memory.c
M softmmu/physmem.c
Log Message:
-----------
memory: Add RAM_PROTECTED flag to skip IOMMU mappings
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Unified the "share" and "protected" arguments with ram_flags in the
memory_region_init_ram_from_fd()(Paolo).
Message-Id: <20210719112136.57018-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0343e22de3bd738855cba901894ad4890d8de447
https://github.com/qemu/qemu/commit/0343e22de3bd738855cba901894ad4890d8de447
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
Log Message:
-----------
hostmem: Add hostmem-epc as a backend for SGX EPC
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
EPC page, hardware performs additional access control checks to
restrict access to the page. After the current page access checks
and translations are performed, the hardware checks that the EPC
page is accessible to the program currently executing. Generally an
EPC page is only accessed by the owner of the executing enclave or
an instruction which is setting up an EPC page.
Because of its unique requirements, Linux manages EPC separately from
normal memory. Similar to memfd, the device /dev/sgx_vepc can be
opened to obtain a file descriptor which can in turn be used to mmap()
EPC memory.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Unified the "share" and "protected" arguments with ram_flags in the
memory_region_init_ram_from_fd()(Paolo).
Message-Id: <20210719112136.57018-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f0c5f92fef60adc248a341137400ab58071f0e6
https://github.com/qemu/qemu/commit/5f0c5f92fef60adc248a341137400ab58071f0e6
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M qapi/qom.json
Log Message:
-----------
qom: Add memory-backend-epc ObjectOptions support
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX since v6.1, or the sgx backend
object cannot bootup.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Added the new MemoryBackendEpcProperties and related documents,
and updated the blurb(Eric Blake).
Message-Id: <20210719112136.57018-4-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: fdb74f3e88397df821783eeeb76fb70215e39e39
https://github.com/qemu/qemu/commit/fdb74f3e88397df821783eeeb76fb70215e39e39
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/meson.build
A hw/i386/sgx-epc.c
A include/hw/i386/sgx-epc.h
Log Message:
-----------
i386: Add 'sgx-epc' device to expose EPC sections to guest
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
been created.
The 'sgx-epc' device is essentially a placholder at this time, it will
be fully implemented in a future patch along with a dedicated command
to create 'sgx-epc' devices.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5ef63c1442d18c465958dc17167c1fcd32729982
https://github.com/qemu/qemu/commit/5ef63c1442d18c465958dc17167c1fcd32729982
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/meson.build
M hw/i386/sgx-epc.c
A hw/i386/sgx.c
M hw/i386/x86.c
M include/hw/i386/pc.h
M include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M qapi/machine.json
M qemu-options.hx
Log Message:
-----------
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Moved sgx compound property setter/getter from MachineState
to X86MachineState(Paolo).
- Re-defined struct SgxEPC, removed 'id' property and added struct
SgxEPCList for sgx-epc.0.{memdev}(Paolo).
- Removed g_malloc0(), and changed the 'SGXEPCState *sgx_epc' to
'SGXEPCState sgx_epc' in struct PCMachineState(Paolo).
- Changed the SGX compound property cmdline from sgx-epc.{memdev}.0
to sgx-epc.0.{memdev}(Paolo).
v2-->v3:
- Removed the QemuOptsList for sgx-epc virtual device and used the '-M' to
replace '-sgx-epc' with compound properties(Paolo).
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c049cf6a723a8d87dc3b39a417e24a8620fe9039
https://github.com/qemu/qemu/commit/c049cf6a723a8d87dc3b39a417e24a8620fe9039
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add primary SGX CPUID and MSR defines
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled (in FEATURE_CONTROL).
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: da37ddad4c20eb8c65ab654e2f1485bcd082f199
https://github.com/qemu/qemu/commit/da37ddad4c20eb8c65ab654e2f1485bcd082f199
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC management
- ENCLV instruction set for VMM oversubscription of EPC
- ENCLS-C instruction set for thread safe variants of ENCLS
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 52f465060438679d73b59530f858db95a6d31008
https://github.com/qemu/qemu/commit/52f465060438679d73b59530f858db95a6d31008
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-9-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d2e73f4f132fda9d0cf3f6a221172129f454dc07
https://github.com/qemu/qemu/commit/d2e73f4f132fda9d0cf3f6a221172129f454dc07
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the enclave has has been initialized by EINIT. Cannot
be set by software, i.e. forced to zero in CPUID.
- DEBUG: permits a debugger to read/write into the enclave.
- MODE64BIT: the enclave runs in 64-bit mode
- PROVISIONKEY: grants has access to the provision key
- EINITTOKENKEY: grants access to the EINIT token key, i.e. the
enclave can generate EINIT tokens
- KSS: Key Separation and Sharing enabled for the enclave.
Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates
the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly
exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all
reserved and bits 127:64 correspond to the allowed XSAVE Feature Request
Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX,
AVX, etc... and is not exposed to the user.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-10-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: db322e208f2a633fc1bf4acb202b03e2bcb7bf1c
https://github.com/qemu/qemu/commit/db322e208f2a633fc1bf4acb202b03e2bcb7bf1c
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/machine.c
Log Message:
-----------
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KVM advertises SGX LC via CPUID if and only if the MSRs are writable.
Unconditionally initialize those MSRs to digest of Intel's signing key
when CPU is realized and reset to reflect the fact. This avoids
potential bug in case kvm_arch_put_registers() is called before
kvm_arch_get_registers() is called, in which case guest's virtual
SGX_LEPUBKEYHASH MSRs will be set to 0, although KVM initializes those
to digest of Intel's signing key by default, since KVM allows those MSRs
to be updated by Qemu to support live migration.
Save/restore the SGX Launch Enclave Public Key Hash MSRs if SGX Launch
Control (LC) is exposed to the guest. Likewise, migrate the MSRs if they
are writable by the guest.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Kai Huang <kai.huang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-11-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 20f94efce81a7934b32a9839e204d87fae39b398
https://github.com/qemu/qemu/commit/20f94efce81a7934b32a9839e204d87fae39b398
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/nvram/fw_cfg.c
Log Message:
-----------
fw_cfg: add etc/msr_feature_control
The file already existed, but nobody had noticed the warning until now.
Add it at the bottom, since that is where unknown files go in legacy mode.
Fixes: 217f1b4a721 ("target-i386: Publish advised value of
MSR_IA32_FEATURE_CONTROL via fw_cfg")
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 64049db9226169e6d461c7969dcc8356cc0f3d5e
https://github.com/qemu/qemu/commit/64049db9226169e6d461c7969dcc8356cc0f3d5e
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Add feature control MSR dependency when SGX is enabled
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-12-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 78d803b230e6cfa93d3db69a2c206e8a09d49669
https://github.com/qemu/qemu/commit/78d803b230e6cfa93d3db69a2c206e8a09d49669
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/sgx.c
M include/hw/i386/sgx-epc.h
M target/i386/cpu.c
Log Message:
-----------
i386: Update SGX CPUID info according to hardware/KVM/user input
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
ultimately emulation will fail as software cannot generate a valid
quote/report. The complexity of partially emulating SGX in Qemu far
outweighs the value added, e.g. an SGX specific simulator for userspace
applications can emulate SGX for development and testing purposes.
Note, access to the PROVISIONKEY is not yet advertised to the guest as
KVM blocks access to the PROVISIONKEY by default and requires userspace
to provide additional credentials (via ioctl()) to expose PROVISIONKEY.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Replaced g_malloc0() with directly ....
Message-Id: <20210719112136.57018-13-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2f13f6466b85393e379043e5eb7cf13102d9d806
https://github.com/qemu/qemu/commit/2f13f6466b85393e379043e5eb7cf13102d9d806
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
Log Message:
-----------
i386: kvm: Add support for exposing PROVISIONKEY to guest
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-14-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: dae4b0b666c4a6f075527cf3ab1418b716107aca
https://github.com/qemu/qemu/commit/dae4b0b666c4a6f075527cf3ab1418b716107aca
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Propagate SGX CPUID sub-leafs to KVM
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic and user
defined, the number of SGX sub-leafs is "NULL" terminated.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-15-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ae9e0315ced5966c1c922f543004561d00fca5c7
https://github.com/qemu/qemu/commit/ae9e0315ced5966c1c922f543004561d00fca5c7
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
Adjust min CPUID level to 0x12 when SGX is enabled
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-16-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bab724bd1e8cdf4f3bd508fed6f1db70181356e2
https://github.com/qemu/qemu/commit/bab724bd1e8cdf4f3bd508fed6f1db70181356e2
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/fw_cfg.c
Log Message:
-----------
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-17-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e69f94c5abcd61f53eb5046856bb45f1b0b7deeb
https://github.com/qemu/qemu/commit/e69f94c5abcd61f53eb5046856bb45f1b0b7deeb
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/sgx-epc.h
Log Message:
-----------
hw/i386/pc: Account for SGX EPC sections when calculating device memory
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity because we don't support EPC NUMA affinity
now. Once the SGX EPC NUMA support in the kernel SGX driver, we will
support this in the future.
Note that SGX EPC is currently hardcoded to reside above 4g.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-18-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a8cb3fca3d3b1a4a0b84fb68bb35786a48491066
https://github.com/qemu/qemu/commit/a8cb3fca3d3b1a4a0b84fb68bb35786a48491066
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/pc: Add e820 entry for SGX EPC section(s)
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-19-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1275344073ffd71f3f22b454bf80c6159847c07e
https://github.com/qemu/qemu/commit/1275344073ffd71f3f22b454bf80c6159847c07e
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
i386: acpi: Add SGX EPC entry to ACPI tables
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI tables,
i.e. software must enumerate the EPC sections via CPUID. Furthermore,
software expects to see only a single EPC Device in the ACPI tables
regardless of the number of EPC sections in the system.
However, several versions of Windows do rely on the ACPI tables to
enumerate the address and size of the EPC. So, regardless of the number
of EPC sections exposed to the guest, create exactly *one* EPC device
with a _CRS entry that spans the entirety of all EPC sections (which are
guaranteed to be contiguous in Qemu).
Note, NUMA support for EPC memory is intentionally not considered as
enumerating EPC NUMA information is not yet defined for bare metal.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-20-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 83055af7d17bec3fab24f79840e11ffb5abed0cc
https://github.com/qemu/qemu/commit/83055af7d17bec3fab24f79840e11ffb5abed0cc
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
q35: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-21-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 157fd04dc618d506fba406be4a9b3dc465681ddc
https://github.com/qemu/qemu/commit/157fd04dc618d506fba406be4a9b3dc465681ddc
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
i440fx: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-22-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 18fb753e8ddc81ef786375b53be9e0a7080246a4
https://github.com/qemu/qemu/commit/18fb753e8ddc81ef786375b53be9e0a7080246a4
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M backends/hostmem-epc.c
M include/hw/i386/pc.h
Log Message:
-----------
hostmem-epc: Add the reset interface for EPC backend reset
Add the sgx_memory_backend_reset() interface to handle EPC backend
reset when VM is reset. This reset function will destroy previous
backend memory region and re-mmap the EPC section for guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-23-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2a6ed8f7c5b5d9a7bb6b79518f9f6d3fce9733f5
https://github.com/qemu/qemu/commit/2a6ed8f7c5b5d9a7bb6b79518f9f6d3fce9733f5
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
Log Message:
-----------
sgx-epc: Add the reset interface for sgx-epc virt device
If the VM is reset, we need make sure sgx virt epc in clean status.
Once the VM is reset, and sgx epc virt device will be reseted by
reset callback registered by qemu_register_reset(). Since this epc
virt device depend on backend, this reset will call backend reset
interface to re-mmap epc to guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-24-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8547c926e7fdd1fcb9f5257970c79d81756c8ee7
https://github.com/qemu/qemu/commit/8547c926e7fdd1fcb9f5257970c79d81756c8ee7
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
Log Message:
-----------
sgx-epc: Avoid bios reset during sgx epc initialization
Since bios do the reset when qemu boot up, and sgx epc will be
reset by the registered reset callback function. Like this, the
sgx epc will do two times initialization. This patch will check
protected mode from cr0 register, and will bypass reset operation
from bios. The reset callback will only accept reset operation
from guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-25-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a9442d4f42788f5e387d761df6bb78dc485b672a
https://github.com/qemu/qemu/commit/a9442d4f42788f5e387d761df6bb78dc485b672a
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M backends/hostmem-epc.c
Log Message:
-----------
hostmem-epc: Make prealloc consistent with qemu cmdline during reset
If qemu cmdline set the prealloc property for sgx epc and VM do the
reset the prealloc property will be different with cmdline settings.
This patch can make sure same prealloc property setting with cmdline.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-26-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0036da471a58875a6d78495af5c1e5f81c3f14e5
https://github.com/qemu/qemu/commit/0036da471a58875a6d78495af5c1e5f81c3f14e5
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M backends/meson.build
M configs/devices/i386-softmmu/default.mak
M hw/i386/Kconfig
M hw/i386/meson.build
A hw/i386/sgx-stub.c
Log Message:
-----------
Kconfig: Add CONFIG_SGX support
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-32-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 98cbe856a7837302131652e96fa7c14e015395c2
https://github.com/qemu/qemu/commit/98cbe856a7837302131652e96fa7c14e015395c2
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
M monitor/hmp-cmds.c
M qapi/machine.json
Log Message:
-----------
sgx-epc: Add the fill_device_info() callback support
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info memory-devices
Memory device [sgx-epc]: ""
memaddr: 0x180000000
size: 29360128
memdev: /objects/mem1
Memory device [sgx-epc]: ""
memaddr: 0x181c00000
size: 10485760
memdev: /objects/mem2
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Removed the epc device 'id' from compound property(Paolo).
v1-->v2:
- "Since: 5.1" to "Since: 6.1"(Eric Blake).
Message-Id: <20210719112136.57018-33-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d8710daf74a9bd2db4fa15a58be4ae2abbe61878
https://github.com/qemu/qemu/commit/d8710daf74a9bd2db4fa15a58be4ae2abbe61878
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M docs/index.rst
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
M docs/tools/qemu-img.rst
M docs/tools/qemu-nbd.rst
M docs/tools/qemu-pr-helper.rst
M docs/tools/qemu-storage-daemon.rst
M docs/tools/qemu-trace-stap.rst
Log Message:
-----------
docs: standardize book titles to === with overline
Documents within a Sphinx manual are separate files and therefore can use
different conventions for headings. However, keeping some consistency is
useful so that included files are easy to get right.
This patch uses a standard heading format for book titles, so that it is
obvious when a file sits at the top level toctree of a book or man page.
The heading is irrelevant for man pages, but keep it consistent as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9da9fb76a7f41ac2a34436375654c02d79367197
https://github.com/qemu/qemu/commit/9da9fb76a7f41ac2a34436375654c02d79367197
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M docs/about/index.rst
M docs/devel/index.rst
M docs/interop/index.rst
M docs/specs/index.rst
M docs/system/index.rst
M docs/tools/index.rst
M docs/user/index.rst
Log Message:
-----------
docs: standardize directory index to --- with overline
Use a standard heading format for the index.rst file in a directory.
Using overlines makes it clear that individual documents can use e.g.
=== for chapter titles and --- for section titles, as suggested in the
Linux kernel guidelines[1]. They could do it anyway, because documents
included in a toctree are parsed separately and therefore are not tied
to the same conventions for headings. However, keeping some consistency is
useful since sometimes files are included from multiple places.
[1] https://www.kernel.org/doc/html/latest/doc-guide/sphinx.html
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 21efff8cda2541a3e1f98644d7ce8caaaeeba71f
https://github.com/qemu/qemu/commit/21efff8cda2541a3e1f98644d7ce8caaaeeba71f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
Log Message:
-----------
docs/system: standardize man page sections to --- with overline
Man pages in docs/system use file inclusion heavily. Use headings with
overlines in the main files, so that the same included file work well
from both manuals and man pages.
This style of heading is a bit more heavy-weight, so it is not used by
the other man pages in interop/ and tools/. If in the future they
are changed to use include files, for example to avoid having sections
named "synopsis" or "description", they can switch to --- with overline
as well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a37d0085017ce0ccf8e000f77bed74fe2e846f25
https://github.com/qemu/qemu/commit/a37d0085017ce0ccf8e000f77bed74fe2e846f25
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M docs/system/cpu-models-x86.rst.inc
A docs/system/i386/cpu.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs/system: move x86 CPU configuration to a separate document
Currently, cpu-models-x86.rst.inc is included in target-i386.rst directly.
To make the toctree more homogeneous when adding more documentation,
include it through a first-class .rst file.
Together with the previous changes to the man page skeletons, this also
frees "===" for the headings, so that cpu-models-x86.rst.inc need not
assume anything about the headings used by target-i386.rst.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8a0eb834698b70d5bb398222ced9516b7e7abc28
https://github.com/qemu/qemu/commit/8a0eb834698b70d5bb398222ced9516b7e7abc28
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
A docs/system/i386/sgx.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs/system: Add SGX documentation to the system manual
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-34-yang.zhong@intel.com>
[Convert to reStructuredText, and adopt the standard === --- ~~~ headings
suggested for example by Linux. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 81d32fa6d4740aee0a69249b0b5165e105a534ce
https://github.com/qemu/qemu/commit/81d32fa6d4740aee0a69249b0b5165e105a534ce
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M meson.build
Log Message:
-----------
meson.build: Do not look for VNC-related libraries if have_system is not set
When running "./configure --static --disable-system" there is currently
a warning if the static version of libpng is missing:
WARNING: Static library 'png16' not found for dependency 'libpng', may not
be statically linked
Since it does not make sense to look for the VNC-related libraries at all
when we're building without system emulator binaries, let's add a check
for have_system here to silence this warning.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210906153939.165567-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3b942628231462c56c883a6273cf137d2a382f8f
https://github.com/qemu/qemu/commit/3b942628231462c56c883a6273cf137d2a382f8f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
M ebpf/meson.build
Log Message:
-----------
ebpf: only include in system emulators
eBPF files are being included in user emulators. That is useless, and
it also breaks --disable-system compilation because ebpf/trace-events is
only processed if a system emulator is included in the build.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/566
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d1e0c5caff3dffcf221fa9c68d74c85f69405a37
https://github.com/qemu/qemu/commit/d1e0c5caff3dffcf221fa9c68d74c85f69405a37
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-08 (Wed, 08 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
M configs/devices/i386-softmmu/default.mak
M docs/about/index.rst
M docs/devel/index.rst
M docs/index.rst
M docs/interop/index.rst
M docs/specs/index.rst
M docs/system/cpu-models-x86.rst.inc
A docs/system/i386/cpu.rst
A docs/system/i386/sgx.rst
M docs/system/index.rst
M docs/system/qemu-block-drivers.rst
M docs/system/qemu-cpu-models.rst
M docs/system/qemu-manpage.rst
M docs/system/target-i386.rst
M docs/tools/index.rst
M docs/tools/qemu-img.rst
M docs/tools/qemu-nbd.rst
M docs/tools/qemu-pr-helper.rst
M docs/tools/qemu-storage-daemon.rst
M docs/tools/qemu-trace-stap.rst
M docs/user/index.rst
M ebpf/meson.build
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/fw_cfg.c
M hw/i386/meson.build
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
A hw/i386/sgx-epc.c
A hw/i386/sgx-stub.c
A hw/i386/sgx.c
M hw/i386/x86.c
M hw/nvram/fw_cfg.c
M hw/vfio/common.c
M include/exec/memory.h
M include/hw/i386/pc.h
A include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M meson.build
M monitor/hmp-cmds.c
M qapi/machine.json
M qapi/qom.json
M qemu-options.hx
M softmmu/memory.c
M softmmu/physmem.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/machine.c
M target/i386/svm.h
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into
staging
* SGX support (Sean, Yang)
* vGIF and vVMLOAD/VMSAVE support (Lara)
* Fix LA57 support in TCG (Daniel)
* Avoid pointless warnings for static user-only compilation (Thomas)
* Fix --disable-system compilation if libbpf is found
* target-i386.rst restructuring
# gpg: Signature made Wed 08 Sep 2021 10:59:36 BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (43 commits)
ebpf: only include in system emulators
meson.build: Do not look for VNC-related libraries if have_system is not set
docs/system: Add SGX documentation to the system manual
docs/system: move x86 CPU configuration to a separate document
docs/system: standardize man page sections to --- with overline
docs: standardize directory index to --- with overline
docs: standardize book titles to === with overline
sgx-epc: Add the fill_device_info() callback support
Kconfig: Add CONFIG_SGX support
hostmem-epc: Make prealloc consistent with qemu cmdline during reset
sgx-epc: Avoid bios reset during sgx epc initialization
sgx-epc: Add the reset interface for sgx-epc virt device
hostmem-epc: Add the reset interface for EPC backend reset
i440fx: Add support for SGX EPC
q35: Add support for SGX EPC
i386: acpi: Add SGX EPC entry to ACPI tables
i386/pc: Add e820 entry for SGX EPC section(s)
hw/i386/pc: Account for SGX EPC sections when calculating device memory
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Adjust min CPUID level to 0x12 when SGX is enabled
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/bd662023e683...d1e0c5caff3d
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