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[Qemu-commits] [qemu/qemu] 4d3344: accel/tcg: Add DisasContextBase argum

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 4d3344: accel/tcg: Add DisasContextBase argument to transl...
Date: Mon, 13 Sep 2021 01:39:59 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4d33449be3fb9d07e5698d732447f16cfdbae571
      
https://github.com/qemu/qemu/commit/4d33449be3fb9d07e5698d732447f16cfdbae571
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M include/exec/translator.h
    M target/alpha/translate.c
    M target/arm/arm_ldst.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/hexagon/translate.c
    M target/hppa/translate.c
    M target/i386/tcg/translate.c
    M target/m68k/translate.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/openrisc/translate.c
    M target/ppc/translate.c
    M target/riscv/translate.c
    M target/s390x/tcg/translate.c
    M target/sh4/translate.c
    M target/sparc/translate.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  accel/tcg: Add DisasContextBase argument to translator_ld*

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
[rth: Split out of a larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: af11924a7d1c72513fc0b221dc717b31c77f6cac
      
https://github.com/qemu/qemu/commit/af11924a7d1c72513fc0b221dc717b31c77f6cac
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M include/exec/translate-all.h
    M include/exec/translator.h

  Log Message:
  -----------
  accel/tcg: Clear PAGE_WRITE before translation

translate_insn() implementations fetch instruction bytes piecemeal,
which can cause qemu-user to generate inconsistent translations if
another thread modifies them concurrently [1].

Fix by making pages containing translated instruction non-writable
right before loading instruction bytes from them.

[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 93c77eaaf80d750aa9e60c8d87f50e846aded219
      
https://github.com/qemu/qemu/commit/93c77eaaf80d750aa9e60c8d87f50e846aded219
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Split P_VEXW from P_REXW

We need to be able to represent VEX.W on a 32-bit host, where REX.W
will always be zero.  Fixes the encoding for VPSLLVQ and VPSRLVQ.

Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 769cbd5b0095694447d8a2e57b3b94621555c413
      
https://github.com/qemu/qemu/commit/769cbd5b0095694447d8a2e57b3b94621555c413
  Author: Luc Michel <lmichel@kalray.eu>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M accel/tcg/tcg-accel-ops-rr.c

  Log Message:
  -----------
  accel/tcg: remove redundant TCG_KICK_PERIOD define

The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
Remove it from tcg-accel-ops-rr.c.

Signed-off-by: Luc Michel <lmichel@kalray.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9714024d7e061f678abf620c8aa53148d5c7d2e0
      
https://github.com/qemu/qemu/commit/9714024d7e061f678abf620c8aa53148d5c7d2e0
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M include/tcg/tcg-op.h
    M target/hppa/translate.c

  Log Message:
  -----------
  tcg: Remove tcg_global_reg_new defines

Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
these tcg_global_reg_new_ macros are not used anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6183c59bbaa7dcc920abab4d9e30c381e18d8925
      
https://github.com/qemu/qemu/commit/6183c59bbaa7dcc920abab4d9e30c381e18d8925
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M include/qemu/bswap.h
    M meson.build

  Log Message:
  -----------
  include/qemu: Use builtins for bswap

All supported compilers have builtins for this.
Drop all of the complicated system detection stuff.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d5f46be194c1e3b7109eedafe95b221aa75ca003
      
https://github.com/qemu/qemu/commit/d5f46be194c1e3b7109eedafe95b221aa75ca003
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN

If __APPLE__, ensure that _CALL_DARWIN is set, then remove
our local TCG_TARGET_CALL_DARWIN.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 77c14b1cb028ca30bf574a5727e58b0c37c91f64
      
https://github.com/qemu/qemu/commit/77c14b1cb028ca30bf574a5727e58b0c37c91f64
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF

Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
the ABI for ppc32.  Make a good guess based on other symbols.

Reported-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118
      
https://github.com/qemu/qemu/commit/267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118
  Author: Jose R. Ziviani <jziviani@suse.de>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Fix tcg_out_vec_op function signature

Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
for arm is missing. It causes a build error on armv6 and armv7:

tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
   const TCGArg *args, const int *const_args)
  ~~~~~~~~~~~~~~^~~~
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
{aka 'const unsigned int[16]'}
   const TCGArg args[TCG_MAX_OP_ARGS],
  ~~~~~~~~~~~~~~^~~~

Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cf6037ff37f677c469c2405e9f5d48a6b814d2a3
      
https://github.com/qemu/qemu/commit/cf6037ff37f677c469c2405e9f5d48a6b814d2a3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M accel/tcg/tcg-accel-ops-rr.c
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M include/exec/translate-all.h
    M include/exec/translator.h
    M include/qemu/bswap.h
    M include/tcg/tcg-op.h
    M meson.build
    M target/alpha/translate.c
    M target/arm/arm_ldst.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/hexagon/translate.c
    M target/hppa/translate.c
    M target/i386/tcg/translate.c
    M target/m68k/translate.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/openrisc/translate.c
    M target/ppc/translate.c
    M target/riscv/translate.c
    M target/s390x/tcg/translate.c
    M target/sh4/translate.c
    M target/sparc/translate.c
    M target/xtensa/translate.c
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210912' into 
staging

Fix translation race condition for user-only.
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
Fix tcg/arm tcg_out_vec_op signature.
Fix tcg/ppc (32bit) build with clang.
Remove dupluate TCG_KICK_PERIOD definition.
Remove unused tcg_global_reg_new.
Use __builtin_bswap*.

# gpg: Signature made Sun 12 Sep 2021 16:52:33 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210912:
  tcg/arm: Fix tcg_out_vec_op function signature
  tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
  tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
  include/qemu: Use builtins for bswap
  tcg: Remove tcg_global_reg_new defines
  accel/tcg: remove redundant TCG_KICK_PERIOD define
  tcg/i386: Split P_VEXW from P_REXW
  accel/tcg: Clear PAGE_WRITE before translation
  accel/tcg: Add DisasContextBase argument to translator_ld*

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/99c44988d5ba...cf6037ff37f6
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