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[Qemu-commits] [qemu/qemu] 8b1d5b: include/exec: Move cpu_signal_handler
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 8b1d5b: include/exec: Move cpu_signal_handler declaration |
Date: |
Thu, 23 Sep 2021 02:19:41 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 8b1d5b3c3507d062d7611a64a81989e8903605ed
https://github.com/qemu/qemu/commit/8b1d5b3c3507d062d7611a64a81989e8903605ed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M include/exec/exec-all.h
M target/alpha/cpu.h
M target/arm/cpu.h
M target/avr/cpu.h
M target/cris/cpu.h
M target/hexagon/cpu.h
M target/hppa/cpu.h
M target/i386/cpu.h
M target/m68k/cpu.h
M target/microblaze/cpu.h
M target/mips/cpu.h
M target/mips/internal.h
M target/nios2/cpu.h
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/riscv/cpu.h
M target/rx/cpu.h
M target/s390x/cpu.h
M target/sh4/cpu.h
M target/sparc/cpu.h
M target/tricore/cpu.h
M target/xtensa/cpu.h
Log Message:
-----------
include/exec: Move cpu_signal_handler declaration
There is nothing target specific about this. The implementation
is host specific, but the declaration is 100% common.
Reviewed-By: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0596fa11f16c81d5237da64e59e8583a971dfe1c
https://github.com/qemu/qemu/commit/0596fa11f16c81d5237da64e59e8583a971dfe1c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Restrict cpu_handle_halt() to sysemu
Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following
comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn():
case EXCP_HALTED:
/* during start-up the vCPU is reset and the thread is
* kicked several times. If we don't ensure we go back
* to sleep in the halted state we won't cleanly
* start-up when the vCPU is enabled.
*
* cpu->halted should ensure we sleep in wait_io_event
*/
g_assert(cpu->halted);
break;
qemu_wait_io_event() is sysemu-specific, so we can restrict the
cpu_handle_halt() call in cpu_exec() to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210912172731.789788-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 10d4af5810ab0250418e34e40be817932f26ff95
https://github.com/qemu/qemu/commit/10d4af5810ab0250418e34e40be817932f26ff95
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Drop inline markers
Let the compiler decide about inlining.
Remove tcg_out_ext8s and tcg_out_ext16s as unused.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d7fc9f48c3056dc1a1e69d095858742f012ae910
https://github.com/qemu/qemu/commit/d7fc9f48c3056dc1a1e69d095858742f012ae910
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr
Weaning off of unique alignment requirements, so allow JAL
to not reach the target. TCG_TMP1 is always available for
use as a scratch because it is clobbered by the subroutine
being called.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5a8f0a5dd2a9dcb60355158d04e8e8a5d41fdec6
https://github.com/qemu/qemu/commit/5a8f0a5dd2a9dcb60355158d04e8e8a5d41fdec6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Unset TCG_TARGET_HAS_direct_jump
Only use indirect jumps. Finish weaning away from the
unique alignment requirements for code_gen_buffer.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3d1e8ed011ee87ab3e4688c1a22f5b909856b0a4
https://github.com/qemu/qemu/commit/3d1e8ed011ee87ab3e4688c1a22f5b909856b0a4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/region.c
Log Message:
-----------
tcg/mips: Drop special alignment for code_gen_buffer
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 897fd616fdb1347b903c81f101f03eb6e6474246
https://github.com/qemu/qemu/commit/897fd616fdb1347b903c81f101f03eb6e6474246
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/sparc/tcg-target.c.inc
Log Message:
-----------
tcg/sparc: Drop inline markers
Let the compiler decide about inlining.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 220b2da7f34c29412db0dc0182e36fce67c8a9e4
https://github.com/qemu/qemu/commit/220b2da7f34c29412db0dc0182e36fce67c8a9e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/sparc/tcg-target.c.inc
Log Message:
-----------
tcg/sparc: Introduce tcg_out_mov_delay
This version of tcg_out_mov is emits a nop to fill the
delay slot if the move is not required.
The only current use, for INDEX_op_goto_ptr, will always
require the move but properly documents the delay slot.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fa947a667fceab02f9f85fc99f54aebcc9ae6b51
https://github.com/qemu/qemu/commit/fa947a667fceab02f9f85fc99f54aebcc9ae6b51
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M include/hw/core/tcg-cpu-ops.h
M target/alpha/cpu.h
M target/arm/internals.h
M target/hppa/cpu.c
M target/microblaze/cpu.h
M target/mips/tcg/tcg-internal.h
M target/nios2/cpu.h
M target/ppc/internal.h
M target/riscv/cpu.h
M target/s390x/s390x-internal.h
M target/sh4/cpu.h
M target/xtensa/cpu.h
Log Message:
-----------
hw/core: Make do_unaligned_access noreturn
While we may have had some thought of allowing system-mode
to return from this hook, we have no guests that require this.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 81c65ee223ba759c15c11068f9b292a59a900451
https://github.com/qemu/qemu/commit/81c65ee223ba759c15c11068f9b292a59a900451
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-21 (Tue, 21 Sep 2021)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Remove add with zero on user-only memory access
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c9fec9b5382b9869130cdc0ff21ddd783d240623
https://github.com/qemu/qemu/commit/c9fec9b5382b9869130cdc0ff21ddd783d240623
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-23 (Thu, 23 Sep 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/exec/exec-all.h
M include/hw/core/tcg-cpu-ops.h
M target/alpha/cpu.h
M target/arm/cpu.h
M target/arm/internals.h
M target/avr/cpu.h
M target/cris/cpu.h
M target/hexagon/cpu.h
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/i386/cpu.h
M target/m68k/cpu.h
M target/microblaze/cpu.h
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/tcg/tcg-internal.h
M target/nios2/cpu.h
M target/openrisc/cpu.h
M target/ppc/cpu.h
M target/ppc/internal.h
M target/riscv/cpu.h
M target/rx/cpu.h
M target/s390x/cpu.h
M target/s390x/s390x-internal.h
M target/sh4/cpu.h
M target/sparc/cpu.h
M target/tricore/cpu.h
M target/xtensa/cpu.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/region.c
M tcg/riscv/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210921' into
staging
Move cpu_signal_handler declaration.
Restrict cpu_handle_halt to sysemu.
Make do_unaligned_access noreturn.
Misc tcg/mips cleanup
Misc tcg/sparc cleanup
Misc tcg/riscv cleanup
# gpg: Signature made Wed 22 Sep 2021 03:47:29 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210921:
tcg/riscv: Remove add with zero on user-only memory access
hw/core: Make do_unaligned_access noreturn
tcg/sparc: Introduce tcg_out_mov_delay
tcg/sparc: Drop inline markers
tcg/mips: Drop special alignment for code_gen_buffer
tcg/mips: Unset TCG_TARGET_HAS_direct_jump
tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr
tcg/mips: Drop inline markers
accel/tcg: Restrict cpu_handle_halt() to sysemu
include/exec: Move cpu_signal_handler declaration
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7b25e776725b...c9fec9b5382b
- [Qemu-commits] [qemu/qemu] 8b1d5b: include/exec: Move cpu_signal_handler declaration,
Peter Maydell <=